Data Sheet
July 2000
LU6612
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management
Basic Operations
The primary function of station management is to transfer control and status information about the LU6612 to a
management entity. This function is accomplished by the MDC clock input, which has a maximum frequency of
12.5 MHz, along with the MDIO pin. The management interface (MII) uses MDC and MDIO to physically transport
information between the PHY and the station management entity.
A specific set of registers and their contents (described in Table 8) defines the nature of the information transferred
across this interface. Frames transmitted on the MII management interface will have the frame structure shown in
Table 6. The order of bit transmission is from left to right. Note that reading and writing of the management register
must be completed without interruption.
MII Management Frames
The fields and format for management frames are described in the following tables.
Table 6. MII Management Frame Fields and Format
Read/Write
Pre
ST
OP
PHYADD
REGAD
TA
DATA
Idle
(R/W)
R
1 . . . 1
1 . . . 1
01
01
10
01
AAAAA
AAAAA
RRRRR
RRRRR
Z0
10
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
W
Table 7. MII Management Frame Descriptions
Field
Description
Pre
Preamble. The preamble is a series of 32 1s. The LU6612 will accept frames with no preamble.
This is indicated by a 1 in register 1, bit 6.
ST
Start of Frame. The start of frame is indicated by a 01 pattern.
OP
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is 01.
PHYADD PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity, which is
attached to multiple PHY entities, must have prior knowledge of the appropriate PHY address for
each entity. The address 00000 is the broadcast address. This address will produce a match
regardless of the local address.
REGAD
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY.
The first register address bit transmitted and received is the MSB of the address.
TA
Turnaround. The turnaround time is a 2-bit time spacing between the register address field and the
data field of a frame to avoid drive contention on MDIO during a read transaction. During a write to
the LU6612, these bits are driven to a 10 by the station. During a read, the MDIO is not driven dur-
ing the first bit time and is driven to a 0 by the LU6612 during the second bit time.
DATA
Data. The data field is 16 bits. The first bit transmitted and received is bit 15 of the register being
addressed.
Lucent Technologies Inc.
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