AD9834
The AD9834 is a sampled signal with its output following
Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that
occur at multiples of the reference clock frequency and the
selected output frequency. A graphical representation of the
sampled spectrum, with aliased images, is shown in Figure 28.
REGULATOR
The AD9834 has separate power supplies for the analog and
digital sections. AVDD provides the power supply required for
the analog section, and DVDD provides the power supply for
the digital section. Both of these supplies can have a value of
2.3 V to 5.5 V and are independent of each other. For example,
the analog section can be operated at 5 V, and the digital section
can be operated at 3 V, or vice versa.
The prominence of the aliased images is dependent on the ratio
of fOUT to MCLK. If ratio is small, the aliased images are very
prominent and of a relatively high energy level as determined
by the sin(x)/x roll-off of the quantized DAC output. In fact,
depending on the fOUT/reference clock relationship, the first
aliased image can be on the order of −3 dB below the
fundamental.
The internal digital section of the AD9834 is operated at 2.5 V.
An on-board regulator steps down the voltage applied at DVDD
to 2.5 V. The digital interface (serial port) of the AD9834 also
operates from DVDD. These digital signals are level shifted
within the AD9834 to make them 2.5 V compatible.
A low-pass filter is generally placed between the output of the
DAC and the input of the comparator to further suppress the
effects of aliased images. Obviously, consideration must be
given to the relationship of the selected output frequency and
the reference clock frequency to avoid unwanted (and unexpected)
output anomalies. To apply the AD9834 as a clock generator,
limit the selected output frequency to <33% of reference clock
frequency, and thereby avoid generating aliased signals that fall
within, or close to, the output band of interest (generally dc-
selected output frequency). This practice eases the complexity
(and cost) of the external filter requirement for the clock
generator application. Refer to the AN-837 Application Note
for more information.
When the applied voltage at the DVDD pin of the AD9834 is
equal to or less than 2.7 V, Pin CAP/2.5V and Pin DVDD should
be tied together, thus bypassing the on-board regulator.
OUTPUT VOLTAGE COMPLIANCE
The AD9834 has a maximum current density, set by the RSET
of 4 mA. The maximum output voltage from the AD9834 is
VDD − 1.5 V. This is to ensure that the output impedance of
the internal switch does not change, affecting the spectral
,
performance of the part. For a minimum supply of 2.3 V, the
maximum output voltage is 0.8 V. Specifications in Table 1 are
guaranteed with an RSET of 6.8 kꢀ and an RLOAD of 200 ꢀ.
To enable the comparator, Bit SIGN/PIB and Bit OPBITEN in
the control resister are set to 1. This is explained further in
Table 17.
fOUT
sin x/x ENVELOPE
x = π (f/fC)
fC – fOUT
fC
+
fOUT
2fC – fOUT
2fC
+
fOUT
3fC – fOUT
fC
2
fC
3
fC + fOUT
3
fC
0Hz
FIRST
IMAGE
SECOND
IMAGE
THIRD
IMAGE
FOURTH
IMAGE
FIFTH
IMAGE
SIXTH
IMAGE
SYSTEM CLOCK
FREQUENCY (Hz)
Figure 28. The DAC Output Spectrum
Rev. C | Page 17 of 36
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