Data Sheet
AD5940
ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 2) Register—ADCGAINGN2
Address 0x00002274, Reset: 0x00004000, Name: ADCGAINGN2
The ADCGAINGN2 register provides gain calibration for the voltage input channels to the ADC, including the AINx channels, when the
PGA is enabled with gain = 2.
Table 64. Bit Descriptions for ADCGAINGN2 Register
Bits
[31:15] Reserved
[14:0] Value
Bit Name Settings Description
Reset
Access
Reserved.
0x0
R
Gain calibration for PGA gain = 2. These bits provide ADC gain correction for the
auxiliary input channels. These bits are used for all channels except the TIA and the
temperature sensor channels when PGA gain = 2. This value is stored as a signed
number. Bit 14 is the sign bit and Bits[13:0] represent the fractional part.
0x4000 R/W
0x0000
0x2000
0x4000
0x4001
0x7FFF
0x0001
0x3FFF
0. Illegal value resulting in an ADC result of 0.
0.5. ADC result multiplied by 0.5.
1.0. ADC result multiplied by 1. No gain adjustment (default value).
1.000061. Minimum positive gain adjustment.
2. Maximum positive gain adjustment.
0.000061. Maximum negative gain adjustment.
0.999939. Minimum negative gain adjustment.
ADC Offset Calibration Auxiliary Input Channel (PGA Gain = 4) Register—ADCOFFSETGN4
Address 0x000022D4, Reset: 0x00000000, Name: ADCOFFSETGN4
The ADCOFFSETGN4 register provides ADC input offset calibration with PGA gain = 4.
Table 65. Bit Descriptions for ADCOFFSETGN4 Register
Bits
Bit Name
Reserved
Value
Settings
Description
Reset
Access
R
[31:15]
[14:0]
Reserved.
0x0
0x0
Offset calibration gain = 4. ADC offset correction with PGA gain = 4.
R/W
0x3FFF 4095.75. Maximum positive offset calibration value.
0x0001 0.25. Minimum positive offset calibration value.
0x0000 0. No offset adjustment.
0x7FFF −0.25. Minimum negative offset calibration value.
0x4000 −4096. Maximum negative offset calibration value.
ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 4) Register—ADCGAINGN4
Address 0x00002278, Reset: 0x00004000, Name: ADCGAINGN4
The ADCGAINGN4 register provides gain calibration for the voltage input channels to the ADC, including the AINx channels, when
PGA is enabled with gain = 4.
Table 66. Bit Descriptions for ADCGAINGN4 Register
Bits
[31:15] Reserved
[14:0] Value
Bit Name
Settings Description
Reset
Access
Reserved.
0x0
R
Gain calibration for PGA gain = 4. These bits provide ADC gain correction for the
0x4000 R/W
auxiliary input channels. These bits are used for all channels except the TIA and
temperature sensor channels when PGA gain = 4. This value is stored as a signed
number. Bit 14 is the sign bit and Bits[13:0] represent the fractional part.
0x0000 0. Illegal value resulting in an ADC result of 0.
0x2000 0.5. ADC result multiplied by 0.5.
0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default value).
0x4001 1.000061. Minimum positive gain adjustment.
0x7FFF 2. Maximum positive gain adjustment.
0x0001 0.000061. Maximum negative gain adjustment.
0x3FFF 0.999939. Minimum negative gain adjustment.
Rev. 0 | Page 63 of 130
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