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EVAL-AD5940BIOZ 参数 Datasheet PDF下载

EVAL-AD5940BIOZ图片预览
型号: EVAL-AD5940BIOZ
PDF下载: 下载PDF文件 查看货源
内容描述: [High Precision, Impedance, and Electrochemical Front End]
分类和应用:
文件页数/大小: 130 页 / 1952 K
品牌: ADI [ ADI ]
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Data Sheet  
AD5940  
ADC Gain Calibration for the High Speed TIA Channel Register—ADCGAINHSTIA  
Address 0x00002284, Reset: 0x00004000, Name: ADCGAINHSTIA  
Table 58. Bit Descriptions for ADCGAINHSTIA Register  
Bits  
Bit Name  
Reserved  
Value  
Settings  
Description  
Reset  
0x0  
Access  
R
[31:15]  
[14:0]  
Reserved.  
Gain error calibration on the high speed TIA channel.  
0x4000  
R/W  
0x7FFF 2. Maximum positive gain adjustment.  
0x4001 1.000061. Minimum positive gain adjustment.  
0x4000 1.0. ADC result multiplied by 1. No gain adjustment (default).  
0x3FFF 0.999939. Minimum negative gain adjustment.  
0x2000 0.5. ADC result multiplied by 0.5.  
0x0001 0.000061. Maximum negative gain adjustment.  
0x0000 0. Illegal value; results in an ADC result of 0.  
ADC Offset Calibration Auxiliary Channel (PGA Gain = 1) Register—ADCOFFSETGN1  
Address 0x00002244, Reset: 0x00000000, Name: ADCOFFSETGN1  
Table 59. Bit Descriptions for ADCOFFSETGN1 Register  
Bits  
[31:15] Reserved  
[14:0] Value  
Bit Name  
Settings Description  
Reset Access  
Reserved.  
0x0  
0x0  
R
Offset calibration gain = 1. ADC offset correction for the auxiliary channel with PGA  
R/W  
gain = 1, represented as a twos complement number. The calibration resolution is  
0.25 LSBs of the ADCDAT LSB size. Therefore, the calibration resolution is VREF/218. If  
V
REF = 1.82 V, the calibration resolution is 1.82/217 = 13.885 μV.  
0x3FFF 4095.75. Maximum positive offset calibration value.  
0x0001 0.25. Minimum positive offset calibration value.  
0x0000 0. No offset adjustment.  
0x7FFF −0.25. Minimum negative offset calibration value.  
0x4000 −4096. Maximum negative offset calibration value.  
ADC Gain Calibration Auxiliary Input Channel (PGA Gain = 1) Register—ADCGAINGN1  
Address 0x00002240, Reset: 0x00004000, Name: ADCGAINGN1  
The ADCGAINGN1 register provides gain calibration for the voltage input channels to the ADC, including the AINx channels.  
Table 60. Bit Descriptions for ADCGAINGN1 Register  
Bits  
[31:15] Reserved  
[14:0] Value  
Bit Name Settings Description  
Reset  
Access  
Reserved.  
0x0  
R
Gain calibration for PGA gain = 1. ADC gain correction for auxiliary input channels.  
These bits are used for all channels, except the TIA and temperature sensor channels  
when PGA gain = 1. This value is stored as a signed number. Bit 14 is the sign bit, and  
Bits[13:0] represent the fractional part.  
0x4000 R/W  
0x0000  
0x2000  
0x4000  
0x4001  
0x7FFF  
0x0001  
0x3FFF  
0. Illegal value; results in an ADC result of 0x8000.  
0.5. ADC result multiplied by 0.5.  
1.0. ADC result multiplied by 1. No gain adjustment (default).  
1.000061. Minimum positive gain adjustment.  
2. Maximum positive gain adjustment.  
0.000061. Maximum negative gain adjustment.  
0.999939. Minimum negative gain adjustment.  
Rev. 0 | Page 61 of 130  
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