AD5940
Data Sheet
Note that disabling the Hanning window can result in degraded
performance.
The gain calibration is optional and adjusts the peak-to-peak
voltage swing. Alternatively, adjust the voltage swing by
changing the maximum and/or minimum DAC code.
HIGH SPEED DAC CALIBRATION OPTIONS
The high speed DAC transfer function is shown in Figure 23.
Figure 24 shows how the common-mode voltage is set by the
noninverting input of the high speed TIA. This voltage must be
set by the low power DAC VZERO0 output or by the internal
1.11 V ADC VBIAS0 voltage.
The high speed DAC is not calibrated during production testing
by Analog Devices. This section describes the steps to calibrate
the high speed DAC for all gain settings and in both high power
and low power modes.
Calibrate the high speed DAC if the DAC is needed to generate
an excitation signal to a sensor. If an offset error exists on the
excitation signal, and a current or voltage output requires
measurement, the excitation signal can exceed the headroom of
the selected TIA, ADC input buffer, or PGA setting.
DAC CODES
OUTPUT VOLTAGE
0xE00
(POSITIVE
FULL SCALE)
DAC VOLTAGE =
COMMON-MODE VOLTAGE
POSITIVE FULL SCALE
OFFSET ERROR
Figure 24 shows the circuit diagram for high speed DAC
calibration. A precision external resistor, RCAL, is required
between the RCAL0 pin and the RCAL1 pin. To calibrate the
offset, the differential voltage measured across the RCAL resistor
must be 0 V.
0x800
(ZERO SCALE)
DAC VOLTAGE =
COMMON-MODE VOLTAGE
0x200
(NEGATIVE
FULL SCALE)
DAC VOLTAGE =
COMMON-MODE VOLTAGE
NEGATIVE FULL SCALE
Calibrate the high speed DAC with the required bit settings
(HSDACCON, Bit 12 and Bit 0). For example, if the DAC is
calibrated with HSDACCON, Bit 12 = 0 and HSDACCON,
Bit 0 = 0, and the user changes HSDACCON, Bit 12 to 1, an
offset error is introduced. Either the DACOFFSET register or
DACOFFSETHS register must be recalibrated for the new
output range.
Figure 23. High Speed DAC Transfer Function
The AD5940 software development kit includes sample
functions that demonstrate how to use the ADC to measure the
differential voltage across the RCAL resistor and how to adjust the
appropriate calibration register until the differential voltage is
~0 V. The AD5940 software development kit is available for
download from the AD5940 product page.
PMBW[0]
PMBW[0]
0
1
0
1
DACOFFSETATTEN
DACOFFSETATTENHS
DACOFFSET
DACOFFSETHS
VREF_1V82
1.0V
G = 1 OR G = 0.2
HSDACCON[0]
fC = 50kHz/100kHz/
HSDACCON[0]
0
1
DACGAIN
250kHz
P
+
HIGH SPEED
DAC
HSDACDAT[11:0]
RCAL0
D
EXCITATION
AMP
PGA
–
RCF
N
0.2V
G = 1 OR 0.25
HSDACCON
[12]
R
DAC CLK
CAL
RCAL1
NEGATIVE NODE
ADC MEASURES
DIFFERENTIAL VOLTAGE
BETWEEN P-NODES AND
N-NODES TO CALIBRATE DAC
HSTIACON[1:0]
SETS
POSITIVE
NODE
VBIAS_CAP
(1.11V)
COMMON-MODE
VOLTAGE
MUX
NEGATIVE
ADC
V
NODE
ZERO
TO ADC
MUX
+
HSTIA
–
Figure 24. High Speed DAC Calibration
Rev. 0 | Page 42 of 130
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