Data Sheet
AD5940
HIGH SPEED DAC CIRCUIT REGISTERS
Table 24. High Speed DAC Control Registers Summary
Address
Name
Description
Reset
Access
R/W
R/W
0x00002010
0x00002048
HSDACCON
HSDACDAT
High speed DAC configuration
High speed DAC code register
0x0000001E
0x00000800
High Speed DAC Configuration Register—HSDACCON
Address 0x00002010, Reset: 0x0000001E, Name: HSDACCON
Table 25. Bit Descriptions for HSDACCON Register
Bits
Bit Name
Settings Description
Reset Access
[31:13] Reserved
Reserved.
0x0
0x0
R
R/W
12
INAMPGNMDE
Excitation amplifier gain control. This bit selects the gain of the excitation amplifier.
0
1
Gain = 2.
Gain = 0.25.
Reserved.
[11:9]
[8:1]
Reserved
Rate
0x0
0xF
R/W
R/W
DAC update rate. DAC update rate = ACLK/HSDACCON, Bits[8:1]. ACLK can be a
high speed oscillator at 16 MHz or 32 MHz, or a low power oscillator at 32 kHz.
0
ATTENEN
PGA stage gain attenuation. Enable the PGA attenuator at the output of the DAC.
DAC attenuator disabled. Gain of 1 mode.
DAC attenuator enabled. Gain of 0.2 mode.
0x0
R/W
0
1
High Speed DAC Code Register—HSDACDAT
Address 0x00002048, Reset: 0x00000800, Name: HSDACDAT
Table 26. Bit Descriptions for HSDACDAT Register
Bits
[31:12] Reserved
[11:0] DACDAT
Bit Name Settings Description
Reset
0x0
0x800 R/W
Access
R
Reserved.
DAC code, written directly to the DAC. The minimum code is 0x200 and the maximum
code is 0xE00. Midscale (0x800) corresponds to an output voltage of 0 V.
Table 27. High Speed DAC Calibration Registers Summary
Address
Name
Description
Reset
Access
0x00002230
0x00002260
0x00002264
0x00002268
0x000022B8
0x000022BC
CALDATLOCK
DACGAIN
DACOFFSETATTEN
DACOFFSET
DACOFFSETATTENHS
DACOFFSETHS
Calibration data lock register
DAC gain register
DAC offset with attenuator enabled (low power mode) register
DAC offset with attenuator disabled (low power mode) register
DAC offset with attenuator enabled (high speed mode) register
DAC offset with attenuator disabled (high speed mode) register
0xDE87A5A0
0x00000800
0x00000000
0x00000000
0x00000000
0x00000000
R/W
R/W
R/W
R/W
R/W
R/W
Table 28. High Speed DAC Calibration Register Assignment
Relevant Calibration Registers
Low Power Mode and
High Speed Mode
HSDACCON Register
Bit Settings
Typical Output Range (mV),
Code 0x200 to Code 0xE00
Low Power Mode High Speed Mode
DACOFFSET
DACOFFSET
DACOFFSETHS
DACOFFSETHS
DACGAIN
DACGAIN
Bit 12 = 0 and Bit 0 = 0
Bit 12 = 1 and Bit 0 = 0
Bit 12 = 1 and Bit 0 = 1
Bit 12 = 0 and Bit 0 = 1
607
75
15.14
121.2
DACOFFSETATTEN DACOFFSETATTENHS DACGAIN
DACOFFSETATTEN DACOFFSETATTENHS DACGAIN
Rev. 0 | Page 43 of 130
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