Data Sheet
AD5940
HIGH SPEED DAC OUTPUT ATTENUATION
OPTIONS
V
BIAS0
BIAS VOLTAGE
(UP TO 600mV)
Scaling options to modify the output signal amplitude to the
sensor are present for the high speed DAC output. The output of
the 12-bit DAC string is ±±33 mꢀ before any attenuation or
gain. At the DAC output, there is a gain stage of 1 or 3.2. At the
PGA stage, there are gain options of 2 or 3.25. Table 28
describes the available gain options and the corresponding
output voltage ranges.
V
ZERO0
Figure 22. Sensor Excitation Signal
COUPLING AN AC SIGNAL FROM THE HIGH SPEED
DAC TO THE DC LEVEL SET BY THE LOW POWER
DAC
The AD5943 contains a low power potentiostat channel to
configure an electrochemical sensor. In normal operation, the
bias voltage of the sensor between the RE3 and SE3 electrodes is
set by the low power DAC outputs, ꢀBIAS3 and ꢀZERO3, where
HIGH SPEED DAC EXCITATION AMPLIFIER
Figure 21 illustrates the operation of the excitation amplifier
and its connection to the switch matrix. There are four inputs to
the excitation amplifier: DACP, DACN, positive (P), and
negative (N). The high speed DAC is a differential output DAC
where the positive and negative inputs feed directly to the
excitation amplifier. The voltage difference between these two
outputs sets the peak-to-peak voltage on the output waveform.
The P and N inputs maintain the stability of the excitation
amplifier by providing a feedback path from the sensor, and set
the common-mode for the high speed DAC output. Under
normal circumstances, the common mode is set by the ꢀZERO3
output connected to the N input. There is also an option to
apply a dc bias voltage to the sensor and couple an ac signal
onto this bias, as shown in Figure 22.
ꢀBIAS3 sets the bias to the potentiostat and the voltage on the
CE3 pin. ꢀZERO3 sets the bias voltage on the low power TIA and the
SE3 pin. The high speed DAC circuit is not used. However, for
ac impedance measurements, the output of the excitation
amplifier must be connected to the CE3 pin. The potentiostat
must be disconnected so that the entire signal comes from the
excitation amplifier output. The high speed TIA is connected to
the SE3 pin and the low power TIA is disconnected. The sensor
bias must then be set by the high speed TIA and the excitation
amplifier.
To set the sensor bias, take the following steps:
An option is available if the sensor requires a bias voltage
between the counter and sense electrode. ꢀBIAS3 sets the voltage
on the counter electrode (the common-mode voltage of the
high speed DAC) and ꢀZERO3 sets the voltage on the sense
electrode. ꢀZERO3 must be connected to the positive terminal on
the high speed TIA (HSTIACON, Bits[1:3] = 31). The dc buffers
of the DAC must also be enabled by setting AFECON, Bit 21.
With this configuration, a waveform can be achieved, as shown
in Figure 22. The bias across the sensor is effectively the
1. The ꢀZERO3 output of the low power DAC must be
connected to the noninverting input of the high speed TIA
(HSTIACON, Bits[1:3] = 31), which sets the voltage on the
SE3 pin, or whichever pin is connected to the inverting
input of the high speed TIA via the switch matrix.
2. The DAC dc buffers must be enabled (AFECON, Bit 21 = 1).
Figure 21 shows the connection of the dc buffers to the
excitation amplifier. These buffers enable the low power
DAC outputs to drive the required bias voltage to the
excitation amplifier and the high speed TIA.
difference between ꢀBIAS3 and ꢀZERO3
.
±. The dc bias is the difference between ꢀBIAS3 and ꢀZERO3
.
Note that the high speed DAC signal chain must never be used
in conjunction with the low power TIA. The high speed DAC
can become unstable, leading to incorrect measurements.
AVOIDING INCOHERENCY ERRORS BETWEEN
EXCITATION AND MEASUREMENT FREQUENCIES
DURING IMPEDANCE MEASUREMENTS
The following settings are recommended to avoid incoherency
errors between excitation and measurement frequencies during
impedance measurements:
R
R
DACP
DACN
D
+
–
12-BIT
DAC
PGA
RCF
The Hanning window is always on (DFTCON, Bit 3 = 1).
In low power mode, the high speed DAC update rate is
16 MHz or 27 MHz (HSDACCON, Bits[8:1] = 3x1B). In
high power mode, the high speed DAC update rate is
±2 MHz or 7 MHz (HSDACCON, Bits[8:1] = 3x7).
In low power mode, the ADC sampling rate is 833 kSPS
(high frequency oscillator = 16 MHz). In high power
mode, the ADC sampling rate is 1.6 MSPS (high frequency
oscillator = ±2 MHz).
P
N
2R
2R
–
+
+
–
V
BIAS0
AFECON[21]
–
+
+
–
V
ZERO0
DAC DC BUFFERS
Figure 21. High Speed DAC Excitation Amplifier
Rev. 0 | Page 41 of 130
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