AD5940
Data Sheet
GPIO Port 0 Registered Data Input—GP0IN
Address 0x00000010, Reset: 0x0000, Name: GP0IN
Table 152. Bit Descriptions for GP0IN Register
Bits
[15:8] Reserved
[7:0] IN
Bit Name Settings Description
Reset Access
Reserved.
0x0
0x0
R
R
Registered data input. Each bit reflects the state of the GPIOx pin if the
corresponding input buffer is enabled. If the pin input buffer is disabled the value
seen is zero.
GPIO Port 0 Data Output Register—GP0OUT
Address 0x00000014, Reset: 0x0000, Name: GP0OUT
Table 153. Bit Descriptions for GP0OUT Register
Bits
[15:8] Reserved
[7:0] OUT
Bit Name Settings Description
Reset Access
Reserved.
0x0
R
Data out. Set by user code to drive the corresponding GPIOx high. Cleared by user to 0x0
drive the corresponding GPIOx low.
R/W
GPIO Port 0 Data Out Set Register—GP0SET
Address 0x00000018, Reset: 0x0000, Name: GP0SET
Table 154. Bit Descriptions for GP0SET Register
Bits
[15:8] Reserved
[7:0] Set
Bit Name Settings Description
Reset Access
Reserved.
0x0
0x0
R
W
Set the output high. Set by user code to drive the corresponding GPIOx high.
Clearing this bit has no effect.
GPIO Port 0 Data Out Clear Register—GP0CLR
Address 0x0000001C, Reset: 0x0000, Name: GP0CLR
Table 155. Bit Descriptions for GP0CLR Register
Bits
[15:8] Reserved
[7:0] CLR
Bit Name Settings Description
Reset Access
Reserved.
0x0
0x0
R
W
Set the output low. Each bit is set to drive the corresponding GPIOx pin low.
Clearing this bit has no effect.
GPIO Port 0 Pin Toggle Register—GP0TGL
Address 0x00000020, Reset: 0x0000, Name: GP0TGL
Table 156. Bit Descriptions for GP0TGL Register
Bits
[15:8] Reserved
[7:0] TGL
Bit Name Settings Description
Reset Access
Reserved
0x0
0x0
R
W
Toggle the Output. Each bit is set to invert the corresponding GPIOx pin. Clearing
this bit has no effect.
Rev. 0 | Page 116 of 130
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