Data Sheet
AD5940
Bits
Bit Name Settings Description
Reset Access
[7:6]
PIN3CFG
PIN2CFG
PIN1CFG
GPIO3 configuration bits.
0x0
0x0
0x0
R/W
R/W
R/W
00 General-purpose input/output.
01 Sequence 3 trigger signal input from the MCU side.
10 Synchronizes External Device 3 output signal.
11 Interrupt 0 output.
[5:4]
[3:2]
GPIO2 configuration bits.
00 POR signal output.
01 Sequence 2 trigger signal input from the MCU side.
10 Synchronizes External Device 2 output signal.
11 External clock input (EXTCLK).
GPIO1 configuration bits.
00 General-purpose input/output.
01 Sequence 1 trigger signal input from the MCU side.
10 Synchronizes External Device 1 output signal.
11 Deep sleep. Sleep flag indicating that the AD5940 is in hibernate mode. Used when
reading data FIFO. When the MCU receives the FIFO full or almost full interrupt, the
MCU waits for this pin to go high. Then, the MCU wakes the AD5940 and reads data
FIFO. After the data FIFO is read, the MCU sends a command to put the AD5940 back
in sleep mode.
[1:0]
PIN0CFG
GPIO0 configuration bits.
0x0
R/W
00 Interrupt 0 output.
01 Sequence 0 trigger signal input from the MCU side.
10 Synchronizes External Device 0 output signal.
11 General-purpose input/output.
GPIO Port 0 Output Enable Register—GP0OEN
Address 0x00000004, Reset: 0x0000, Name: GP0OEN
The GP0OEN register enables the output for each GPIO.
Table 149. Bit Descriptions for GP0OEN Register
Bits
[15:8] Reserved
[7:0] OEN
Bit Name Settings Description
Reset Access
Reserved.
0x0
0x0
R
R/W
Pin output drive enable. Each bit in this range is set to enable the output for that
particular pin. Each bit is cleared to disable the output for each pin.
GPIO Port 0 Pull-Up and Pull-Down Enable Register—GP0PE
Address 0x00000008, Reset: 0x0000, Name: GP0PE
Table 150. Bit Descriptions for GP0PE Register
Bits
[15:8] Reserved
[7:0] PE
Bit Name
Settings Description
Reset Access
Reserved.
0x0
0x0
R
R/W
Pin pull enable. Each bit in this range is set to enable the pull-up and/or pull-down
resistor for that particular pin. Each bit is cleared to disable the pull-up/pull-down resistor
for each pin.
GPIO Port 0 Input Path Enable Register—GP0IEN
Address 0x0000000C, Reset: 0x0000, Name: GP0IEN
Table 151. Bit Descriptions for GP0IEN Register
Bits
[15:8] RESERVED
[7:0] IEN
Bit Name
Settings Description
Reset Access
Reserved.
0x0
R
Input path enable. Each bit is set to enable the input path and cleared to disable the 0x0
input path for the GPIOx pin.
R/W
Rev. 0 | Page 115 of 130
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