Data Sheet
AD5940
Bits
Bit Name
Settings
Description
Reset
Access
[10:8]
IRQ6MDE
External Interrupt 6 mode bits.
0x0
R/W
000 Rising edge.
001 Falling edge.
010 Rising or falling edge.
011 High level.
100 Low level.
101 Falling edge (same as 001).
110 Rising or falling edge (same as 010).
111 High level (same as 011).
7
IRQ5EN
External Interrupt 5 enable bit. Set this bit before placing the device in hibernate mode
to enable the ability of GPIO5 to wake up the device.
External Interrupt 5 disabled.
External Interrupt 5 enabled.
External Interrupt 5 mode bits.
0x0
0x0
R/W
R/W
0
1
[6:4]
IRQ5MDE
000 Rising edge.
001 Falling edge.
010 Rising or falling edge.
011 High level.
100 Low level.
101 Falling edge (same as 001).
110 Rising or falling edge (same as 010).
111 High level (same as 011).
3
IRQ4EN
External Interrupt 4 enable bit. Set this bit before placing the device in hibernate mode
to enable the ability of GPIO4 to wake up the device.
External Interrupt 4 disabled.
External Interrupt 4 enabled.
External Interrupt 4 mode bits.
0x0
0x0
R/W
R/W
0
1
[2:0]
IRQ4MDE
000 Rising edge.
001 Falling edge.
010 Rising or falling edge.
011 High level.
100 Low level.
101 Falling edge (same as 001).
110 Rising or falling edge (same as 010).
111 High level (same as 011).
External Interrupt Configuration 2 Register—EI2CON
Address 0x00000A28, Reset: 0x0000, Name: EI2CON
Table 144. Bit Descriptions for EI2CON Register
Bits
Bit Name
Settings
Description
Reset Access
[15:4] Reserved
Reserved.
0x0
0x0
R
3
BUSINTEN
Bus interrupt detection enable bit. Set this bit before placing the device in hibernate
mode to enable the ability of the SPI to wake up the device.
R/W
0
1
Bus interrupt wake-up disabled.
Bus interrupt wake-up enabled.
Bus interrupt detection mode bits.
[2:0]
BUSINTMDE
0x0
R/W
000 Rising edge.
001 Falling edge.
010 Rising or falling edge.
011 High level.
100 Low level.
101 Falling edge (same as 001).
110 Rising or falling edge (same as 010).
111 High level (same as 011).
Rev. 0 | Page 111 of 130
ADI [ ADI ]
