Data Sheet
AD5940
Analog Generation Interrupt Register—AFEGENINTSTA
Address 0x0000209C, Reset: 0x00000010, Name: AFEGENINTSTA
The AFEGENINTSTA register provides custom interrupt generation. Writing to this register is only possible using the sequencer. Writing
to this register using the SPI has no effect. Reading this register using the SPI does not return meaningful data.
Table 140. Bit Descriptions for AFEGENINTSTA Register
Bits
Bit Name
Settings Description
Reset Access
[31:4] Reserved
Reserved.
0x1
0x0
R
3
2
1
0
CUSTOMINT3
General-Purpose Custom Interrupt 3. Set this bit manually using the sequencer
program. Write 1 to this bit to trigger an interrupt.
R/W1C
CUSTOMINT2
CUSTOMINT1
CUSTOMINT0
General-Purpose Custom Interrupt 2. Set this bit manually using the sequencer
program. Write 1 to this bit to trigger an interrupt.
0x0
0x0
0x0
R/W1C
R/W1C
R/W1C
General-Purpose Custom Interrupt 1. Set this bit manually using the sequencer
program. Write 1 to this bit to trigger an interrupt.
General-Purpose Custom Interrupt 0. Set this bit manually using the sequencer
program. Write 1 to this bit to trigger an interrupt.
EXTERNAL INTERRUPT CONFIGURATION REGISTERS
Table 141. External Interrupt Registers Summary
Address
Name
Description
Reset
Access
0x00000A20
0x00000A24
0x00000A28
0x00000A30
EI0CON
EI1CON
EI2CON
EICLR
External Interrupt Configuration 0 register
External Interrupt Configuration 1 register
External Interrupt Configuration 2 register
External interrupt clear register
0x0000
0x0000
0x0000
0xC000
R/W
R/W
R/W
R/W
External Interrupt Configuration 0 Register—EI0CON
Address 0x00000A20, Reset: 0x0000, Name: EI0CON
Table 142. Bit Descriptions for EI0CON Register
Bits
Bit Name Settings Description
Reset
Access
15
IRQ3EN
External Interrupt 3 enable bit. Set this bit before placing the device in hibernate
0x0
R/W
mode to enable the ability of GPIO3 to wake up the device.
External Interrupt 3 disabled.
External Interrupt 3 enabled.
0
1
[14:12] IRQ3MDE
External Interrupt 3 mode bits.
0x0
R/W
000 Rising edge.
001 Falling edge.
010 Rising or falling edge.
011 High level.
100 Low level.
101 Falling edge (same as 001).
110 Rising or falling edge (same as 010).
111 High level (same as 011).
11
IRQ2EN
External Interrupt 2 enable bit. Set this bit before placing the device in hibernate
mode to enable the ability of GPIO2 to wake up the device.
External Interrupt 2 disabled.
External Interrupt 2 enabled.
External Interrupt 2 mode bits.
0x0
0x0
R/W
R/W
0
1
[10:8]
IRQ2MDE
000 Rising edge.
001 Falling edge.
010 Rising or falling edge.
011 High level.
100 Low level.
Rev. 0 | Page 109 of 130
ADI [ ADI ]
