AD5940
Data Sheet
Bits
12
Bit Name
Settings Description
Custom Interrupt 3 status.
Reset Access
FLAG12
FLAG11
FLAG10
FLAG9
FLAG8
FLAG7
FLAG6
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R
R
R
R
R
R
0
1
Interrupt not asserted.
Interrupt asserted.
11
10
9
Custom Interrupt 2 status.
Interrupt not asserted.
Interrupt asserted.
Custom Interrupt 1 status.
Interrupt not asserted.
Interrupt asserted.
Custom Interrupt 0 status.
Interrupt not asserted.
Interrupt asserted.
Variance IRQ status.
Interrupt not asserted.
Interrupt asserted.
0
1
0
1
0
1
8
0
1
7
Mean IRQ status.
Interrupt not asserted.
Interrupt asserted.
0
1
6
ADC delta fail IRQ status. When this bit is set, it is indicated that the difference between
two consecutive ADC results is greater than the value specified by the ADCDELTA
register. If this bit is clear, it is indicated that no difference between two consecutive
ADC values greater than the limit is detected since the last time this bit was cleared.
0
1
Interrupt not asserted.
Interrupt asserted.
5
4
FLAG5
FLAG4
ADC maximum fail IRQ status. When this bit is set, it is indicated that an ADC result is 0x0
above the maximum value specified by the ADCMAX register. If this bit is clear, it is
indicated that no ADC value above the maximum is detected.
Interrupt not asserted.
Interrupt asserted.
R
R
0
1
ADC minimum fail IRQ status. When this bit is set, it is indicated that an ADC result is
below the minimum value as specified by the ADCMIN register. If this bit is clear, it is
indicated that no ADC value below the limit is detected since the last time this bit
was cleared.
0x0
0
1
Interrupt not asserted.
Interrupt asserted.
3
2
1
0
FLAG3
FLAG2
FLAG1
FLAG0
Temperature result IRQ status.
Interrupt not asserted.
Interrupt asserted.
Sinc2 filter result ready IRQ status.
Interrupt not asserted.
Interrupt asserted.
DFT result IRQ status.
Interrupt not asserted.
Interrupt asserted.
ADC result IRQ status.
Interrupt not asserted.
Interrupt asserted.
0x0
0x0
0x0
0x0
R
R
R
R
0
1
0
1
0
1
0
1
Rev. 0 | Page 108 of 130
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