AD5940
Data Sheet
INTERRUPT REGISTERS
Table 135. Interrupt Registers Summary
Address
Name
INTCPOL
INTCCLR
INTCSEL0
INTCSEL1
INTCFLAG0
INTCFLAG1
AFEGENINTSTA
Description
Interrupt polarity register
Interrupt clear register
Interrupt controller select register (INT0)
Interrupt controller select register (INT1)
Interrupt controller flag register (INT0)
Interrupt controller flag register (INT1)
Analog generation interrupt
Reset
Access
R/W
W
R/W
R/W
R
0x00003000
0x00003004
0x00003008
0x0000300C
0x00003010
0x00003014
0x0000209C
0x00000000
0x00000000
0x00002000
0x00002000
0x00000000
0x00000000
0x00000010
R
R/W1C
Interrupt Polarity Register—INTCPOL
Address 0x00003000, Reset: 0x00000000, Name: INTCPOL
Table 136. Bit Descriptions for INTCPOL Register
Bits
[31:1]
0
Bit Name
Reserved
INTPOL
Settings
Description
Reserved.
Interrupt polarity.
Reset
0x0
0x0
Access
R
R/W
0
1
Output negative edge interrupt.
Output positive edge interrupt.
Interrupt Clear Register—INTCCLR
Address 0x00003004, Reset: 0x00000000, Name: INTCCLR
Table 137. Bit Descriptions for INTCCLR Register
Bits
31
30
29
28
27
26
25
24
23
22
17
16
15
14
13
12
11
10
9
Bit Name
INTCLR31
Reserved
INTCLR29
Reserved
INTCLR27
INTCLR26
INTCLR25
INTCLR24
INTCLR23
Reserved
INTCLR17
INTCLR16
INTCLR15
Reserved
INTCLR13
INTCLR12
INTCLR11
INTCLR10
INTCLR9
INTCLR8
INTCLR7
INTCLR6
INTCLR5
INTCLR4
INTCLR3
INTCLR2
INTCLR1
INTCLR0
Settings
Description
Attempt to break interrupt (IRQ). Write 1 to clear.
Reserved.
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
Outlier IRQ. Write 1 to clear.
Reserved.
Data FIFO underflow IRQ. Write 1 to clear.
Data FIFO overflow IRQ. Write 1 to clear.
Data FIFO threshold IRQ. Write 1 to clear.
Data FIFO empty IRQ. Write 1 to clear.
Data FIFO full IRQ. Write 1 to clear.
Reserved.
Sequencer timeout error IRQ. Write 1 to clear.
Sequencer timeout finished IRQ. Write 1 to clear.
End of sequence IRQ. Write 1 to clear.
Reserved.
Boot load done IRQ. Write 1 to clear.
Custom Interrupt 3 (IRQ3). Write 1 to clear.
Custom Interrupt 2 (INR. Write 1 to clear.
Custom Interrupt 1. Write 1 to clear.
Custom Interrupt 0. Write 1 to clear.
Variance IRQ. Write 1 to clear.
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
8
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
W
W
W
W
W
W
W
W
W
7
Mean IRQ. Write 1 to clear.
6
ADC delta fail IRQ. Write 1 to clear.
ADC maximum fail IRQ. Write 1 to clear.
ADC minimum fail IRQ. Write 1 to clear.
Temperature result IRQ. Write 1 to clear.
Sinc2 filter result ready IRQ. Write 1 to clear.
DFT result IRQ. Write 1 to clear.
5
4
3
2
1
0
ADC result IRQ. Write 1 to clear.
Rev. 0 | Page 104 of 130
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