ADV7390/ADV7391/ADV7392/ADV7393
Table 16. Register 0x30
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Note
0x30
ED/HD Mode
Register 1
ED/HD Output Standard.
0
0
EIA-770.2 output
EIA-770.3 output
ED
HD
0
1
1
0
EIA-770.1 output
Output levels for full
input range
1
1
Reserved
ED/HD Input
Synchronization Format.
0
1
External
,
HSYNC VSYNC
and field inputs1
Embedded EAV/SAV
codes
ED/HD Input Mode.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
SMPTE 293M, ITU-BT.1358 525p @ 59.94 Hz
Nonstandard timing mode
BTA-1004, ITU-BT.1362
ITU-BT.1358
ITU-BT.1362
525p @ 59.94 Hz
625p @ 50 Hz
625p @ 50 Hz
SMPTE 296M-1,
SMPTE 274M-2
720p @
60 Hz/59.94 Hz
0
0
0
0
1
1
1
1
0
1
SMPTE 296M-3
SMPTE 296M-4,
SMPTE 274M-5
720p @ 50 Hz
720p @
30 Hz/29.97 Hz
0
0
1
1
0
0
0
0
0
1
SMPTE 296M-6
SMPTE 296M-7,
SMPTE 296M-8
720p @ 25 Hz
720p @
24 Hz/23.98 Hz
0
1
0
1
0
SMPTE 240M
1035i @
60 Hz/59.94 Hz
0
0
0
1
1
1
0
1
1
1
0
0
1
0
1
Reserved
Reserved
SMPTE 274M-4,
SMPTE 274M-5
1080i @
30 Hz/29.97 Hz
0
0
1
1
1
1
1
1
0
1
SMPTE 274M-6
SMPTE 274M-7,
SMPTE 274M-8
1080i @ 25 Hz
1080p @
30 Hz/29.97 Hz
1
1
0
0
0
0
0
0
0
1
SMPTE 274M-9
SMPTE 274M-10,
SMPTE 274M-11
1080p @ 25 Hz
1080p @
24 Hz/23.98 Hz
1
0
0
1
0
ITU-R BT.709-5
Reserved
1080Psf @ 24 Hz
10011 to 11111
1 Synchronization can be controlled with a combination of either
and
inputs or
and field inputs, depending on Subaddress 0x34, Bit 6.
HSYNC
HSYNC
VSYNC
Rev. 0 | Page 28 of 96
ADI [ ADI ]
