ADV7390/ADV7391/ADV7392/ADV7393
Table 15. Register 0x0B to Register 0x17
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
7
0
0
0
…
0
6
0
0
0
…
0
5
0
0
0
…
1
4
0
3
0
2
0
0
0
…
1
1
0
0
1
…
1
0
0
1
0
…
1
Register Setting
0%
+0.018%
+0.036%
…
0x0B
DAC 1, DAC 2,
DAC 3 Output
Level
Positive Gain to DAC Output Voltage.
0
0
0
0
…
1
…
1
+7.382%
+7.5%
0
1
0
0
0
0
0
0
Negative Gain to DAC Output
Voltage.
1
1
1
…
1
1
1
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
0
…
1
0
0
1
…
1
0
1
0
…
1
−7.5%
−7.382%
−7.364%
…
−0.018%
0x0D
DAC Power
Mode
DAC 1 Low Power Mode.
DAC 2 Low Power Mode.
DAC 3 Low Power Mode.
SD/ED Oversample Rate Select.
Reserved.
0
1
DAC 1 low power disabled 0x00
DAC 1 low power enabled
DAC 2 low power disabled
DAC 2 low power enabled
DAC 3 low power disabled
DAC 3 low power enabled
SD = 16×, ED = 8×
0
1
0
1
0
1
SD = 8×, ED = 4×
0
0
0
0
0x10
Cable Detection DAC 1 Cable Detect.
Read Only.
0
1
Cable detected on DAC 1 0x00
DAC 1 unconnected
DAC 2 Cable Detect.
Read Only.
0
1
Cable detected on DAC 2
DAC 2 unconnected
Reserved.
0
0
x
Unconnected DAC auto power-down.
0
1
DAC auto power-down
disable
DAC auto power-down
enable
Reserved.
0
x
0
x
0
x
0x13
Pixel Port
P[7:0] Readback (ADV7390/ADV7391).
x
x
x
x
x
x
Read only
0xXX
Readback A1
P[15:8] Readback (ADV7392/ADV7393).
P[7:0] Readback (ADV7392/ADV7393).
0x14
0x16
Pixel Port
x
x
x
x
x
x
x
x
x
Read only
Read only
0xXX
0xXX
Readback B1
Control Port
Readback1
Reserved.
VSYNC
HSYNC
x
Readback.
Readback.
x
SFL/MISO Readback.
Reserved.
x
x
x
0x17
Software Reset
Reserved.
0
0x00
Software Reset.
0
1
Writing a 1 resets the
device; this is a self-
clearing bit
Reserved.
0
0
0
0
0
0
1 For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.
Rev. 0 | Page 27 of 96
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