ADV7390/ADV7391/ADV7392/ADV7393
SDA
SCL
S
P
9
1–7
9
9
1–7
8
8
1–7
8
START ADDR R/W ACK SUBADDRESS ACK
DATA
ACK
STOP
Figure 47. I2C Data Transfer
WRITE
S
S
SLAVE ADDR A(S)
LSB = 0
SUBADDR
SUBADDR
A(S)
DATA
A(S)
DATA
A(M)
A(S) P
SEQUENCE
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S)
A(S)
S
SLAVE ADDR A(S)
DATA
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
Figure 48. I2C Read and Write Sequence
SPI OPERATION
The ADV739x supports a 4-wire serial (SPI-compatible) bus
connecting multiple peripherals. Two inputs, master out slave in
(MOSI) and serial clock (SCLK), and one output, master in
slave out (MISO), carry information between a master SPI
peripheral on the bus and the ADV739x. Each slave device on
the bus has a slave select pin that is connected to the master SPI
peripheral by a unique slave select line. As such, slave device
addressing is not required.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. The user can also
access any unique subaddress register on a one-by-one basis.
In a write data transfer, 8-bit data bytes are written to the
ADV739x, MSB first, on the MOSI line immediately after the
starting subaddress. The data bytes are clocked into the
ADV739x on the rising edge of SCLK. When all data bytes have
To invoke SPI operation, a master SPI peripheral (for example, a
microprocessor) should issue three low pulses on the ADV739x
been written, the master completes the transfer by driving and
SPI_SS
holding the ADV739x ALSB/
In a read data transfer, after the subaddress has been clocked in
SPI_SS
pin high.
SPI_SS
edge on the ALSB/
ALSB/
pin. When the encoder detects the third rising
SPI_SS
pin, it automatically switches to SPI
on the MOSI line, the ALSB/
for at least one clock cycle. Then, the ALSB/
and held low again. On the first SCLK rising edge after
SPI_SS
pin is driven and held high
communication mode. The ADV739x remains in SPI commu-
nication mode until a hardware reset or power-down occurs.
SPI_SS
pin is driven
To control the ADV739x, use the following protocol for both read
and write transactions. First, the master initiates a data transfer by
ALSB/
has been driven low, the read command, defined
as 0xD5, is written, MSB first, to the ADV739x over the MOSI
line. Subsequently, 8-bit data bytes are read from the ADV739x,
MSB first, on the MISO line. The data bytes are clocked out of
the part on the falling edge of SCLK. When all data bytes have
been read, the master completes the transfer by driving and
SPI_SS
driving and holding the ADV739x ALSB/
pin low. On the
SPI_SS
first SCLK rising edge after ALSB/
has been driven low,
the write command, defined as 0xD4, is written to the ADV739x
over the MOSI line. The second byte written to the MOSI line is
interpreted as the starting subaddress. Data on the MOSI line is
written MSB first and clocked on the rising edge of SCLK.
SPI_SS
holding the ADV739x ALSB/
pin high.
Rev. 0 | Page 24 of 96
ADI [ ADI ]
