ADV7390/ADV7391/ADV7392/ADV7393
Table 18. Register 0x34 to Register 0x38
SR7 to
Bit Number
Reset
Value
0x48
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Register Setting
0x34
ED/HD Mode
Register 5
ED/HD Timing Reset.
Internal ED/HD timing counters enabled
Resets the internal ED/HD timing counters
1
HSYNC
VSYNC
0
1
HSYNC
ED/HD
ED/HD
Control.
output control (refer to Table 50)
1
0
1
VSYNC
Control.
output control (refer to Table 51)
Reserved.
1
ED Macrovision Enable.2
0
1
ED Macrovision disabled
ED Macrovision enabled
0 must be written to this bit
Reserved.
0
VSYNC
0
1
0 = Field input
ED/HD
Input.
Input/Field
VSYNC
1 =
input
ED/HD Horizontal/Vertical
Counter Mode.3
0
1
Update field/line counter
Field/line counter free running
0x35
ED/HD Mode
Register 6
Reserved.
0
0x00
Reserved.
0
ED/HD Sync on PrPb.
0
1
Disabled
Enabled
ED/HD Color DAC Swap.
0
1
DAC 2 = Pb, DAC 3 = Pr
DAC 2 = Pr, DAC 3 = Pb
Gamma Correction Curve A
Gamma Correction Curve B
Disabled
ED/HD Gamma Correction
Curve Select.
0
1
ED/HD Gamma
Correction Enable.
0
1
Enabled
ED/HD Adaptive
Filter Mode.
0
1
Mode A
Mode B
ED/HD Adaptive
Filter Enable.
0
1
x
x
x
Disabled
Enabled
0x36
0x37
0x38
ED/HD Y Level4
ED/HD Cr Level4
ED/HD Test Pattern Y Level.
ED/HD Test Pattern Cr Level.
ED/HD Cb Level4 ED/HD Test Pattern Cb Level.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Y level value
0xA0
0x80
0x80
Cr level value
Cb level value
1 Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
2 Applies to the ADV7390 and ADV7392 only.
3 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
4 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Rev. 0 | Page 30 of 96
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