ADV7390/ADV7391/ADV7392/ADV7393
Table 17. Register 0x31 to Register 0x33
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
0
1
Register Setting
Pixel data valid off
Pixel data valid on
4×
0x31
ED/HD Mode
Register 2
ED/HD Pixel Data Valid.
HD Oversample Rate Select.
ED/HD Test Pattern Enable.
ED/HD Test Pattern Hatch/Field.
0
1
2×
0
1
HD test pattern off
HD test pattern on
Hatch
0
1
Field/frame
Disabled
ED/HD Vertical Blanking Interval (VBI)
Open.
0
1
Enabled
ED/HD Undershoot Limiter.
0
0
1
1
0
1
0
1
Disabled
−11 IRE
−6 IRE
−1.5 IRE
ED/HD Sharpness Filter.
0
1
Disabled
Enabled
0x32
ED/HD Mode
Register 3
ED/HD Y Delay with Respect to Falling
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
4 clock cycles
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
4 clock cycles
Disabled
0x00
HSYNC
Edge of
.
ED/HD Color Delay with Respect to
HSYNC
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Falling Edge of
.
ED/HD CGMS Enable.
0
1
Enabled
ED/HD CGMS CRC Enable.
ED/HD Cr/Cb Sequence.
0
1
Disabled
Enabled
0x33
ED/HD Mode
Register 4
0
1
HSYNC
HSYNC
0x68
Cb after falling edge of
Cr after falling edge of
Reserved.
0
0 must be written to this bit
8-bit input
10-bit input1
ED/HD Input Format.
0
1
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
0
1
Disabled
Enabled
Reserved.
0
0 must be written to this bit
Disabled
Enabled
ED/HD Chroma SSAF Filter.
0
1
Reserved.
1
1 must be written to this bit
Disable
Enabled
ED/HD Double Buffering.
0
1
1 Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. 0 | Page 29 of 96
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