ADV7390/ADV7391/ADV7392/ADV7393
Table 14. Register 0x01 to Register 0x09
SR7 to
Bit Number
Reset
Value
0x00
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
0x01
Mode Select
Register
Reserved.
0
DDR Clock Edge Alignment.
Note: Only used for ED1 and
HD DDR modes.
0
0
Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
0
1
1
1
0
1
Reserved.
0
Input Mode.
Note: See Reg. 0x30, Bits[7:3]
for ED/HD format selection.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SD input.
ED/HD-SDR input2
ED/HD-DDR input.
Reserved.
Reserved.
Reserved.
Reserved.
ED (at 54 MHz) input.
Reserved.
0
0x02
Mode
Register 0
Reserved.
Test Pattern Black Bar.3
0
0
Zero must be written to these bits.
Disabled.
Enabled.
0x20
0
1
Manual RGB Matrix Adjust.
Sync on RGB.
0
1
Disable manual RGB matrix adjust.
Enable manual RGB matrix adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
0
1
RGB/YPrPb Output Select.
SD Sync Output Enable.
ED/HD Sync Output Enable.
0
1
0
1
HSYNC
VSYNC
Output SD syncs on
No sync output.
and
pins.
0
1
HSYNC
VSYNC
Output ED/HD syncs on
pins.
and
0x03
0x04
ED/HD CSC
Matrix 0
x
x
x
x
LSBs for GY.
0x03
0xF0
ED/HD CSC
Matrix 1
LSBs for RV.
LSBs for BU.
LSBs for GV.
LSBs for GU.
Bits[9:2] for GY.
x
x
x
x
x
x
x
x
0x05
0x06
0x07
0x08
0x09
ED/HD CSC
Matrix 2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0x4E
0x0E
0x24
0x92
0x7C
ED/HD CSC
Matrix 3
x
x
x
x
x
x
x
x
Bits[9:2] for GU.
Bits[9:2] for GV.
Bits[9:2] for BU.
Bits[9:2] for RV.
ED/HD CSC
Matrix 4
ED/HD CSC
Matrix 5
ED/HD CSC
Matrix 6
1 ED = enhanced definition = 525p and 625p.
2 Available on the ADV7392/ADV7393 (40-pin devices) only.
3 Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
Rev. 0 | Page 26 of 96
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