ADV7390/ADV7391/ADV7392/ADV7393
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
R
1
2
3
4
5
6
7
8
24
V
DD_IO
P2
P3
SET
R
SET
PIN 1
DD_IO
P4
1
2
30
PIN 1
INDICATOR
INDICATOR
23 COMP
22 DAC 1
21 DAC 2
20 DAC 3
29 COMP
28 DAC 1
27 DAC 2
26 DAC 3
P5
3
P6
4
ADV7392/
ADV7393
TOP VIEW
(Not to Scale)
P4
ADV7390/
ADV7391
TOP VIEW
(Not to Scale)
P7
DD
5
V
DD
V
6
25 V
AA
DGND
P5
19
18 AGND
17 PV
V
7
24
23
22
21
AGND
DGND
AA
8
P8
PV
DD
9
P9
EXT_LF
PGND
P6
DD
10
P10
Figure 17. ADV7390/ADV7391 Pin Configuration
Figure 18. ADV7392/ADV7393 Pin Configuration
Table 12. Pin Function Descriptions
Pin Number
ADV7390/91 ADV7392/93
Input/
Output Description
Mnemonic
9 to 7, 4 to 2,
31, 30
P7 to P0
I
8-Bit Pixel Port (P7 to P0). P0 is the LSB. Refer to Table 30 for input
modes (ADV7390/ADV7391).
18 to 15, 11 to 8, 5 P15 to P0
to 2, 39 to 37, 34
I
16-Bit Pixel Port (P15 to P0). P0 is the LSB. Refer to Table 31 for input
modes (ADV7392/ADV7393).
13
27
19
CLKIN
I
Pixel Clock Input for HD (74.25 MHz), ED1 (27 MHz or 54 MHz), or
SD (27 MHz).
Horizontal Synchronization Signal. This pin can also be configured to
output an SD, ED, or HD horizontal synchronization signal. See the
External Horizontal and Vertical Synchronization Control section.
33
HSYNC
I/O
26
25
24
32
31
30
VSYNC
SFL/MISO
RSET
I/O
I/O
I
Vertical Synchronization Signal. This pin can also be configured to
output an SD, ED, or HD vertical synchronization signal. See the
External Horizontal and Vertical Synchronization Control section.
Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data
Output (MISO). The SFL input is used to drive the color subcarrier
DDS system, timing reset, or subcarrier reset.
Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For
full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor
must be connected from RSET to AGND. For low drive operation (for
example, into a 300 Ω load), a 4.12 kΩ resistor must be connected
from RSET to AGND.
23
22, 21, 20
12
11
10
29
28, 27, 26
14
13
12
COMP
DAC 1, DAC 2, DAC 3
SCL/MOSI
SDA/SCLK
ALSB/SPI_SS
O
O
I
I/O
I
Compensation Pin. Connect a 2.2 nF capacitor from COMP to VAA.
DAC Outputs. Full-drive and low-drive capable DACs.
Multifunctional Pin: I2C Clock Input/SPI Data Input.
Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input.
Multifunctional Pin: ALSB sets up the LSB2 of the MPU I2C
address/SPI slave select (SPI_SS).
14
20
RESET
I
Resets the on-chip timing generator and sets the ADV739x into its
default mode.
19
5, 28
25
6, 35
VAA
VDD
P
P
Analog Power Supply (3.3 V).
Digital Power Supply (1.8 V). For dual-supply configurations, VDD can
be connected to other 1.8 V supplies through a ferrite bead or
suitable filtering.
1
17
1
23
VDD_IO
PVDD
P
P
Input/Output Digital Power Supply (3.3 V).
PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can
be connected to other 1.8 V supplies through a ferrite bead or
suitable filtering.
Rev. 0 | Page 16 of 96
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