ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
MISO (Master In, Slave Out) Pin
Table 116. COMIID1 MMR Bit Descriptions
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
Bit 3:1
Status
Bits
Bit 0
Clearing
Operation
NINT Priority Definition
000
110
1
0
No interrupt
2
3
Matching network Read COMRX
address
MOSI (Master Out, Slave In) Pin
101
0
Address
transmitted,
buffer empty
Write data to
COMTX or
read COMIID0
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
011
010
001
0
0
0
1
2
3
Receive line status Read
interrupt
COMSTA0
Receive buffer full Read COMRX
interrupt
SCLK (Serial Clock I/O) Pin
Transmit buffer
empty interrupt
Write data to
COMTX or
read COMIID0
Read
COMSTA1
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI SCLK
period. Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
000
0
4
Modem status
interrupt
Note that to receive a network address interrupt, the slave must
ensure that Bit 0 of COMIEN0 (enable receive buffer full interrupt)
is set to 1.
In master mode, the polarity and phase of the clock are
controlled by the SPICON register, and the bit rate is defined
in the SPIDIV register as follows:
Table 117. COMADR Register
Name
Address
Default Value
Access
fUCLK
2×(1+ SPIDIV)
fSERIAL CLOCK
=
COMADR
0xFFFF0728
0xAA
R/W
COMADR is an 8-bit, read/write network address register that
holds the address checked for by the network addressable
UART. Upon receiving this address, the device interrupts the
processor and/or sets the appropriate status bit in COMIID1.
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 118.
Table 118. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
0
1
2
3
4
5
SERIAL PERIPHERAL INTERFACE
SPIDIV in Hex 0x05
0x0B
0x17
0x2F
0x5F
0xBF
The ADuC7019/20/21/22/24/25/26/27/28/29 integrate a complete
hardware serial peripheral interface (SPI) on-chip. SPI is an
industry standard, synchronous serial interface that allows eight
bits of data to be synchronously transmitted and simultaneously
received, that is, full duplex up to a maximum bit rate of 3.48 Mb,
as shown in Table 118. The SPI interface is not operational with
core clock divider (CD) bits. POWCON[2:0] = 6 or 7 in master
mode.
SPI dpeed
in MHz
3.482 1.741 0.870 0.435 0.218 0.109
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10.4 Mb at CD = 0.
The formula to determine the maximum speed is as follows:
fHCLK
4
fSERIAL CLOCK
=
The SPI port can be configured for master or slave operation.
and typically consists of four pins: MISO (P1.5), MOSI (P1.6),
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
CS
SCLK (P1.4), and
(P1.7).
On the transmit side, the SPITX register (and a TX shift register
outside it) loads data onto the transmit pin (in slave mode,
MISO; in master mode, MOSI). The transmit status bit, Bit 0,
in SPISTA indicates whether there is valid data in the SPITX
register.
Chip Select ( Input) Pin
CS
CS
In SPI slave mode, a transfer is initiated by the assertion of
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
,
Similarly, the receive data path consists of the SPIRX register
(and an RX shift register). SPISTA, Bit 3 indicates whether there
is valid data in the SPIRX register. If valid data in the SPIRX
register is overwritten or if valid data in the RX shift register is
discarded, SPISTA, Bit 5 (the overflow bit) is set.
CS
CS
deassertion of . In slave mode,
is always an input.
Rev. F | Page 74 of 104
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