ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 90. GPxCLR MMR Bit Descriptions
Table 85. GPxDAT Registers
Bit
Description
Name
Address
Default Value1
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
R/W
31:24
23:16
Reserved.
GP0DAT
GP1DAT
GP2DAT
GP3DAT
GP4DAT
1 X = 0, 1, 2, or 3.
0xFFFFF420
0xFFFFF430
0xFFFFF440
0xFFFFF450
0xFFFFF460
Data Port x clear bit. Set to 1 by user to clear bit on
Port x; also clears the corresponding bit in the GPxDAT
MMR. Cleared to 0 by user; does not affect the data out.
R/W
R/W
R/W
15:0
Reserved.
R/W
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals
(an SPI, UART, and two I2Cs) and the programmable logic array
(PLA) to a set of 10 GPIO pins. Each pin must be configured to
one of its specific I/O functions as described in Table 91.
GPxDAT are Port x configuration and data registers. They
configure the direction of the GPIO pins of Port x, set the
output value for the pins configured as output, and store the
input value of the pins configured as input.
Table 91. SPM Configuration
Table 86. GPxDAT MMR Bit Descriptions
GPIO
(00)
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
P2.0
UART
(01)
UART/I2C/SPI PLA
Bit
Description
SPMMUX
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
(10)
(11)
31:24
Direction of the data. Set to 1 by user to configure
the GPIO pin as an output. Cleared to 0 by user to
configure the GPIO pin as an input.
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SCLK
MISO
MOSI
CS
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[4]
PLAO[5]
23:16
15:8
7:0
Port x data output.
Reflect the state of Port x pins at reset (read only).
Port x data input (read only).
Table 87. GPxSET Registers
Name
Address
Default Value1
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
GP0SET
GP1SET
GP2SET
GP3SET
GP4SET
1 X = 0, 1, 2, or 3.
0xFFFFF424
0xFFFFF434
0xFFFFF444
0xFFFFF454
0xFFFFF464
W
W
W
W
W
ECLK/XCLK
CONV
SIN
SOUT
Table 91 also details the mode for each of the SPMMUX pins.
This configuration must be done via the GP0CON, GP1CON,
and GP2CON MMRs. By default, these 10 pins are configured
as GPIOs.
GPxSET are data set Port x registers.
UART SERIAL INTERFACE
Table 88. GPxSET MMR Bit Descriptions
The UART peripheral is a full-duplex, universal, asynchronous
receiver/transmitter. It is fully compatible with the 16,450 serial
port standard. The UART performs serial-to-parallel conversions
on data characters received from a peripheral device or modem,
and parallel-to-serial conversions on data characters received
from the CPU. The UART includes a fractional divider for baud
rate generation and has a network addressable mode. The UART
function is made available on the 10 pins of the ADuC7019/20/
21/22/24/25/26/27/28/29 (see Table 92).
Bit
Description
31:24
23:16
Reserved.
Data Port x set bit. Set to 1 by user to set bit on Port x;
also sets the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data out.
15:0
Reserved.
Table 89. GPxCLR Registers
Name
Address
Default Value1
0x000000XX
0x000000XX
0x000000XX
0x000000XX
0x000000XX
Access
GP0CLR
GP1CLR
GP2CLR
GP3CLR
GP4CLR
1 X = 0, 1, 2, or 3.
0xFFFFF428
0xFFFFF438
0xFFFFF448
0xFFFFF458
0xFFFFF468
W
W
W
W
W
Table 92. UART Signal Description
Pin
Signal
Description
SPM0 (Mode 1)
SPM1 (Mode 1)
SPM2 (Mode 1)
SPM3 (Mode 1)
SPM4 (Mode 1)
SPM5 (Mode 1)
SPM6 (Mode 1)
SPM7 (Mode 1)
SPM8 (Mode 2)
SPM9 (Mode 2)
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
SIN
Serial receive data.
Serial transmit data.
Request to send.
Clear to send.
Ring indicator.
Data carrier detect.
Data set ready.
Data terminal ready.
Serial receive data.
Serial transmit data.
GPxCLR are data clear Port x registers.
SOUT
Rev. F | Page 70 of 104
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