ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
The GDCLK value can range from 0 to 255, corresponding to a
programmable chopping frequency rate of 40.8 kHz to 10.44 MHz
for a 41.78 MHz core frequency. The gate drive features must be
programmed before operation of the PWM controller and are
typically not changed during normal operation of the PWM
controller. Following a reset, all bits of the PWMCFG register
are cleared so that high frequency chopping is disabled, by default.
PWM MMRs Interface
The PWM block is controlled via the MMRs described in
this section.
Table 66. PWMCON Register
Name
Address
Default Value
Access
PWMCON
0xFFFFFC00
0x0000
R/W
PWMCH0
PWMCH0
PWMCON is a control register that enables the PWM and
chooses the update rate.
0L
0H
Table 67. PWMCON MMR Bit Descriptions
2 × PWMDAT1
2 × PWMDAT1
Bit
7:5
4
Name
Description
Reserved.
External sync select. Set to use external
sync. Cleared to use internal sync.
External sync select. Set to select
external synchronous sync signal.
Cleared for asynchronous sync signal.
Double update mode. Set to 1 by user
to enable double update mode.
Cleared to 0 by the user to enable
single update mode.
PWM_SYNCSEL
PWM_EXTSYNC
4 × (GDCLK + 1) × tCORE
PWMDAT0
PWMDAT0
3
2
Figure 72. Typical PWM Signals with High Frequency Gate Chopping
Enabled on Both High-Side and Low-Side Switches
PWMDBL
PWM Shutdown
In the event of external fault conditions, it is essential that the
PWM system be instantaneously shut down in a safe fashion. A
low level on the PWMTRIP pin provides an instantaneous,
asynchronous (independent of the MicroConverter core clock)
shutdown of the PWM controller. All six PWM outputs are
placed in the off state, that is, in low state. In addition, the
PWMSYNC pulse is disabled. The PWMTRIP pin has an internal
pull-down resistor to disable the PWM if the pin becomes
disconnected. The state of the PWMTRIP pin can be read from
Bit 3 of the PWMSTA register.
1
0
PWM_SYNC_EN
PWMEN
PWM synchronization enable. Set by
user to enable synchronization. Cleared
by user to disable synchronization.
PWM enable bit. Set to 1 by user to
enable the PWM. Cleared to 0 by user
to disable the PWM. Also cleared
automatically with PWMTRIP
(PWMSTA MMR).
Table 68. PWMSTA Register
If a PWM shutdown command occurs, a PWMTRIP interrupt is
generated, and internal timing of the 3-phase timing unit of the
PWM controller is stopped. Following a PWM shutdown, the
PWM can be reenabled (in a PWMTRIP interrupt service
routine, for example) only by writing to all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers. Provided that
the external fault is cleared and the PWMTRIP is returned to a
high level, the internal timing of the 3-phase timing unit
resumes, and new duty-cycle values are latched on the next
PWMSYNC boundary.
Name
Address
Default Value
Access
PWMSTA
0xFFFFFC04
0x0000
R/W
PWMSTA reflects the status of the PWM.
Table 69. PWMSTA MMR Bit Descriptions
Bit
15:10
9
Name
Description
Reserved.
PWMSYNCINT PWM sync interrupt bit. Writing a 1 to
this bit clears this interrupt.
PWMTRIPINT PWM trip interrupt bit. Writing a 1 to
this bit clears this interrupt.
8
Note that the PWMTRIP interrupt is available in IRQ only,
and the PWMSYNC interrupt is available in FIQ only. Both
interrupts share the same bit in the interrupt controller.
Therefore, only one of the interrupts can be used at a time.
See the Interrupt System section for further details.
3
2:1
0
PWMTRIP
Raw signal from the PWMTRIP pin.
Reserved.
PWM phase bit. Set to 1 by the Micro-
Converter when the timer is counting
down (first half). Cleared to 0 by the
MicroConverter when the timer is
counting up (second half).
PWMPHASE
Rev. F | Page 66 of 104
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