Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 70. PWMCFG Register
Table 74. PWMDAT0 Register
Name
Address
Default Value
Access
Name
Address
Default Value
Access
PWMCFG
0xFFFFFC10
0x0000
R/W
PWMDAT0
0xFFFFFC08
0x0000
R/W
PWMCFG is a gate chopping register.
PWMDAT0 is an unsigned 16-bit register for switching period.
Table 71. PWMCFG MMR Bit Descriptions
Table 75. PWMDAT1 Register
Bit
15:10
9
8
7:0
Name
Description
Name
Address
Default Value
Access
Reserved.
PWMDAT1
0xFFFFFC0C
0x0000
R/W
CHOPLO
CHOPHI
GDCLK
Low-side gate chopping enable bit.
High-side gate chopping enable bit.
PWM gate chopping period (unsigned).
PWMDAT1 is an unsigned 10-bit register for dead time.
Table 76. PWMCHx Registers
Name
Address
Default Value
0x0000
Access
R/W
Table 72. PWMEN Register
PWMCH0
PWMCH1
PWMCH2
0xFFFFFC14
0xFFFFFC18
0xFFFFFC1C
Name
Address
Default Value
Access
0x0000
R/W
PWMEN
0xFFFFFC20
0x0000
R/W
0x0000
R/W
PWMEN allows enabling of channel outputs and crossover. See
its bit definitions in Table 73.
PWMCH0, PWMCH1, and PWMCH2 are channel duty cycles
for the three phases.
Table 73. PWMEN MMR Bit Descriptions
Table 77. PWMDAT2 Register
Bit Name
Description
Name
Address
Default Value
Access
8
7
6
0H0L_XOVR Channel 0 output crossover enable bit.
Set to 1 by user to enable Channel 0 output
crossover. Cleared to 0 by user to disable
Channel 0 output crossover.
1H1L_XOVR Channel 1 output crossover enable bit.
Set to 1 by user to enable Channel 1 output
crossover. Cleared to 0 by user to disable
Channel 1 output crossover.
2H2L_XOVR Channel 2 output crossover enable bit.
Set to 1 by user to enable Channel 2 output
crossover. Cleared to 0 by user to disable
Channel 2 output crossover.
PWMDAT2
0xFFFFFC24
0x0000
R/W
PWMDAT2 is an unsigned 10-bit register for PWM sync
pulse width.
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7019/20/21/22/24/25/26/27/28/29 provide 40 general-
purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V
tolerant, meaning the GPIOs support an input voltage of 5 V.
In general, many of the GPIO pins have multiple functions (see
Table 78 for the pin function definitions). By default, the GPIO
pins are configured in GPIO mode.
5
4
3
2
1
0
0L_EN
0H_EN
1L_EN
1H_EN
2L_EN
2H_EN
0L output enable bit. Set to 1 by user to
disable the 0L output of the PWM. Cleared to 0
by user to enable the 0L output of the PWM.
0H output enable bit. Set to 1 by user to
disable the 0H output of the PWM. Cleared to
0 by user to enable the 0H output of the PWM.
1L output enable bit. Set to 1 by user to
disable the 1L output of the PWM. Cleared to 0
by user to enable the 1L output of the PWM.
1H Output Enable Bit. Set to 1 by user to
disable the 1H output of the PWM. Cleared to
0 by user to enable the 1H output of the PWM.
2L output enable bit. Set to 1 by user to
disable the 2L output of the PWM. Cleared to 0
by user to enable the 2L output of the PWM.
2H output enable bit. Set to 1 by user to
disable the 2H output of the PWM. Cleared to
0 by user to enable the 2H output of the PWM.
All GPIO pins have an internal pull-up resistor (of about
100 kΩ), and their drive capability is 1.6 mA. Note that a
maximum of 20 GPIOs can drive 1.6 mA at the same time.
Using the GPxPAR registers, it is possible to enable/disable
the pull-up resistors for the following ports: P0.0, P0.4, P0.5,
P0.6, P0.7, and the eight GPIOs of P1.
The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x).
Each port is controlled by four or five MMRs.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. Otherwise, P0.6 goes low for the reset period. For
example, if MRST is required for power-down, it can be
reconfigured in GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7019/20/21/22/24/25/26/27/28/29 part enters a
power-saving mode, the GPIO pins retain their state.
Rev. F | Page 67 of 104
ADI [ ADI ]
