ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 99. COMDIV1 Register
Table 104. COMCON1 Register
Name
Address
Default Value
Access
Name
Address
Default Value
0x00
Access
COMDIV1
0xFFFF0704
0x00
R/W
COMCON1
0xFFFF0710
R/W
COMDIV1 is a divisor latch (high byte) register.
COMCON1 is the modem control register.
Table 100. COMIID0 Register
Table 105. COMCON1 MMR Bit Descriptions
Name
Address
Default Value
Access
Bit Name
Description
COMIID0
0xFFFF0708
0x01
R
7:5
Reserved.
4
LOOPBACK Loopback. Set by user to enable loopback
mode. In loopback mode, SOUT (see Table 78)
is forced high. The modem signals are also
directly connected to the status inputs (RTS
to CTS and DTR to DSR). Cleared by user to
be in normal mode.
COMIID0 is the interrupt identification register.
Table 101. COMIID0 MMR Bit Descriptions
Bit 2:1
Status Bits NINT Priority
Bit 0
Clearing
Operation
Definition
00
11
1
0
N/A
No interrupt N/A
3
2
PEN
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no
parity transmission or checking.
1 (Highest) Receive line
status
Read
COMSTA0
interrupt
STOP
Stop bit. Set by user to transmit 1.5 stop bits
if the word length is five bits, or 2 stop bits if
the word length is six bits, seven bits, or
eight bits. The receiver checks the first stop
bit only, regardless of the number of stop bits
selected. Cleared by user to generate 1 stop
bit in the transmitted data.
10
01
0
0
2
3
Receive
buffer full
interrupt
Transmit
buffer
Read
COMRX
Write data to
COMTX or
read
empty
interrupt
4 (Lowest) Modem
status
COMIID0
Read
COMSTA1
1
0
RTS
DTR
Request to send. Set by user to force the RTS
output to 0. Cleared by user to force the RTS
output to 1.
Data terminal ready. Set by user to force the
DTR output to 0. Cleared by user to force the
DTR output to 1.
00
0
interrupt
Table 102. COMCON0 Register
Name
Address
Default Value
Access
Table 106. COMSTA0 Register
COMCON0
0xFFFF070C
0x00
R/W
Name
Address
Default Value
Access
COMCON0 is the line control register.
COMSTA0
0xFFFF0714
0x60
R
Table 103. COMCON0 MMR Bit Descriptions
COMSTA0 is the line status register.
Bit
Name
Description
Table 107. COMSTA0 MMR Bit Descriptions
Bit Name Description
7
DLAB
Divisor latch access. Set by user to enable access
to the COMDIV0 and COMDIV1 registers. Cleared
by user to disable access to COMDIV0 and
COMDIV1 and enable access to COMRX and
COMTX.
Set break. Set by user to force SOUT to 0. Cleared
to operate in normal mode.
Stick parity. Set by user to force parity to defined
values: 1 if EPS = 1 and PEN = 1,
0 if EPS = 0 and PEN = 1.
Even parity select bit. Set for even parity. Cleared
for odd parity.
Parity enable bit. Set by user to transmit and
check the parity bit. Cleared by user for no parity
transmission or checking.
Stop bit. Set by user to transmit 1.5 stop bits if the
word length is five bits or 2 stop bits if the word
length is six bits, seven bits, or eight bits. The
receiver checks the first stop bit only, regardless
of the number of stop bits selected. Cleared by user
to generate 1 stop bit in the transmitted data.
7
6
Reserved.
TEMT
THRE
COMTX and shift register empty status bit. Set
automatically if COMTX and shift register are
empty. Cleared automatically when writing to
COMTX.
COMTX empty. Set automatically if COMTX is
empty. Cleared automatically when writing to
COMTX.
6
5
BRK
SP
5
4
3
EPS
4
3
2
1
0
BI
Break error. Set when SIN is held low for more than
the maximum word length. Cleared automatically.
Framing error. Set when an invalid stop bit occurs.
Cleared automatically.
Parity error. Set when a parity error occurs.
Cleared automatically.
Overrun error. Set automatically if data is over-
written before being read. Cleared automatically.
PEN
FE
PE
OE
DR
2
STOP
WLS
Data ready. Set automatically when COMRX is full.
Cleared by reading COMRX.
1:0
Word length select:
00 = five bits, 01 = six bits, 10 = seven bits,
11 = eight bits.
Rev. F | Page 72 of 104
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