Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 83. GPIO Drive Strength Control Bits Descriptions
Table 84. GPxPAR Control Bits Access Descriptions
Control Bits Value
Description
Bit
GP0PAR
Reserved
R/W
R/W
Reserved
R/W
R/W
Reserved
R/W
GP1PAR
Reserved
R/W
R/W
Reserved
R/W
00
01
1x
3.6
Medium drive strength.
Low drive strength.
High drive strength.
31
30 to 29
28
27
26 to 25
24
23
22 to 21
20
19
18 to 17
16
15
14 to 13
12
11
3.4
3.2
3.0
2.8
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
Reserved
R (b00)
R/W
2.6
2.4
2.2
2.0
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
10 to 9
8
7
6 to 5
4
3
Figure 73. Programmable Strength for High Level
(Typical Values)
0.5
0.4
0.3
Reserved
R (b00)
R/W
2 to 1
0
0.2
0.1
0
–0.1
–0.2
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
–0.3
–0.4
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
Figure 74. Programmable Strength for Low Level
(Typical Values)
The drive strength bits can be written to one time only after
reset. More writing to related bits has no effect on changing
drive strength. The GPIO drive strength and pull-up disable is
not always adjustable for the GPIO port. Some control bits
cannot be changed (see Table 84).
Rev. F | Page 69 of 104
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