Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
ADC CIRCUIT OVERVIEW
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 49.
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to
1 MSPS when the clock source is 41.78 MHz. This block
provides the user with a multichannel multiplexer, a differential
track-and-hold, an on-chip reference, and an ADC.
1111 1111 1111
1111 1111 1110
1111 1111 1101
The ADC consists of a 12-bit successive approximation converter
based around two capacitor DACs. Depending on the input
signal configuration, the ADC can operate in one of three modes.
1111 1111 1100
FS
1LSB =
4096
Fully differential mode, for small and balanced signals
Single-ended mode, for any single-ended signals
Pseudo differential mode, for any single-ended signals,
taking advantage of the common-mode rejection offered
by the pseudo differential input
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
0V 1LSB
+FS – 1LSB
The converter accepts an analog input range of 0 V to VREF when
operating in single-ended or pseudo differential mode. In fully
differential mode, the input signal must be balanced around a
common-mode voltage (VCM) in the 0 V to AVDD range with a
maximum amplitude of 2 VREF (see Figure 48).
VOLTAGE INPUT
Figure 49. ADC Transfer Function in Pseudo Differential or Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN– input voltage pins (that
is, VIN+ − VIN–). The maximum amplitude of the differential
signal is, therefore, –VREF to +VREF p-p (that is, 2 × VREF). This is
regardless of the common mode (CM). The common mode is
the average of the two signals, for example, (VIN+ + VIN–)/2, and
is, therefore, the voltage that the two inputs are centered on.
This results in the span of each input being CM VREF/2. This
voltage has to be set up externally, and its range varies with VREF
(see the Driving the Analog Inputs section).
AV
DD
V
2V
CM
REF
V
CM
2V
REF
V
2V
CM
REF
0
Figure 48. Examples of Balanced Signals in Fully Differential Mode
A high precision, low drift, factory calibrated, 2.5 V reference is
provided on-chip. An external reference can also be connected as
described in the Band Gap Reference section.
The output coding is twos complement in fully differential mode
with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when
VREF = 2.5 V. The output result is 11 bits, but this is shifted by 1
to the right. This allows the result in ADCDAT to be declared as a
signed integer when writing C code. The designed code
transitions occur midway between successive integer LSB values
(that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS − 3/2 LSB). e ideal
input/output transfer characteristic is shown in Figure 50.
Single or continuous conversion modes can be initiated in the
CONVSTART
software. An external
pin, an output generated from
the on-chip PLA, or a Timer0 or Timer1 overflow can also be
used to generate a repetitive trigger for ADC conversions.
A voltage output from an on-chip band gap reference propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexer, effectively an additional ADC channel
input. This facilitates an internal temperature sensor channel
that measures die temperature to an accuracy of 3°C.
SIGN
BIT
0
0
0
1111 1111 1110
1111 1111 1100
1111 1111 1010
2 × V
4096
REF
1LSB =
0
0
1
0000 0000 0010
0000 0000 0000
1111 1111 1110
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range
is 0 V to VREF. The output coding is straight binary in pseudo
differential and single-ended modes with
1
1
1
0000 0000 0100
0000 0000 0010
0000 0000 0000
1 LSB = FS/4096, or
–V
+ 1LSB
0LSB
+V
– 1LSB
REF
REF
2.5 V/4096 = 0.61 mV, or
610 μV when VREF = 2.5 V
VOLTAGE INPUT (V + – V –)
IN
IN
Figure 50. ADC Transfer Function in Differential Mode
Rev. F | Page 45 of 104
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