ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
0xFFFFFFFF
0xFFFFFC3C
Table 16. Complete MMR List
Access
Byte Type
Default
Value
PWM
0xFFFFFC00
Address Name
Page
0xFFFFF820
IRQ Address Base = 0xFFFF0000
FLASH CONTROL
INTERFACE
0x0000
0x0004
0x0008
0x000C
0x0010
0x0100
0x0104
0x0108
0x010C
IRQSTA
IRQSIG1
IRQEN
IRQCLR
SWICFG
FIQSTA
FIQSIG1
FIQEN
4
4
4
4
4
4
4
4
4
R
R
R/W
W
W
R
R
R/W
W
0x00000000
0x00XXX000 83
0x00000000
0x00000000
0x00000000
0x00000000
0x00XXX000 84
0x00000000
0x00000000
83
0xFFFFF800
0xFFFFF46C
GPIO
83
83
84
84
0xFFFFF400
0xFFFF0B54
PLA
0xFFFF0B00
0xFFFF0A14
SPI
0xFFFF0A00
84
84
FIQCLR
0xFFFF0948
I2C1
1 Depends on the level on the external interrupt pins (P0.4, P0.5, P1.4, and P1.5).
0xFFFF0900
0xFFFF0848
I2C0
System Control Address Base = 0xFFFF0200
0xFFFF0800
0x0220
0x0230
0x0234
REMAP
RSTSTA
RSTCLR
1
1
1
R/W
R/W
W
0xXX1
0x01
0x00
55
55
55
0xFFFF0730
UART
0xFFFF0700
0xFFFF0620
1 Depends on the model.
DAC
0xFFFF0600
Timer Address Base = 0xFFFF0300
0xFFFF0538
ADC
0x0300
0x0304
0x0308
0x030C
0x0320
0x0324
0x0328
0x032C
0x0330
0x0340
0x0344
0x0348
0x034C
0x0360
0x0364
0x0368
0x036C
T0LD
2
2
2
1
4
4
2
1
4
4
4
2
1
2
2
2
1
R/W
R
R/W
W
R/W
R
R/W
W
R/W
R/W
R
R/W
W
R/W
R
R/W
W
0x0000
0xFFFF
0x0000
0xFF
0x00000000
0xFFFFFFFF
0x0000
85
85
85
85
86
86
86
87
87
87
87
87
88
88
88
88
89
0xFFFF0500
T0VAL
T0CON
T0CLRI
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
T2LD
T2VAL
T2CON
T2CLRI
T3LD
T3VAL
T3CON
T3CLRI
0xFFFF0490
BAND GAP
REFERENCE
0xFFFF048C
0xFFFF0448
POWER SUPPLY
MONITOR
0xFFFF0440
0xFFFF0420
PLL AND
OSCILLATOR CONTROL
0xFF
0xFFFF0404
0x00000000
0x00000000
0xFFFFFFFF
0x0000
0xFF
0x0000
0xFFFF
0x0000
0x00
0xFFFF0370
WATCHDOG
TIMER
0xFFFF0360
0xFFFF0350
WAKE-UP
TIMER
0xFFFF0340
0xFFFF0334
GENERAL-PURPOSE
TIMER
0xFFFF0320
0xFFFF0310
TIMER 0
0xFFFF0300
0xFFFF0238
REMAP AND
SYSTEM CONTROL
PLL Base Address = 0xFFFF0400
0xFFFF0220
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
POWKEY1
POWCON
POWKEY2
PLLKEY1
PLLCON
2
2
2
2
1
2
W
R/W
W
W
R/W
W
0x0000
0x0003
0x0000
0x0000
0x21
60
60
60
60
60
60
0xFFFF0110
INTERRUPT
CONTROLLER
0xFFFF0000
Figure 47. Memory Mapped Registers
PLLKEY2
0x0000
PSM Address Base = 0xFFFF0440
0x0440
0x0444
PSMCON
CMPCON
2
2
R/W
R/W
0x0008
0x0000
57
58
Rev. F | Page 42 of 104
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