ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Table 27. ADCOF Register
Table 22. ADCCN MMR Bit Designation
Name
Address
Default Value
0x0200
Access
Bit
7:5
4:0
Value
Description
ADCOF
0xFFFF0534
R/W
Reserved.
Negative channel selection bits.
ADCOF is a 10-bit offset calibration register.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
ADC0.
ADC1.
ADC2.
ADC3.
ADC4.
ADC5.
ADC6.
ADC7.
ADC8.
ADC9.
ADC10.
ADC11.
DAC0/ADC12.
DAC1/ADC13.
DAC2/ADC14.
DAC3/ADC15.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three modes: differential, pseudo
differential, and single-ended.
Differential Mode
The ADuC7019/20/21/22/24/25/26/27/28/29 each contain a
successive approximation ADC based on two capacitive DACs.
Figure 54 and Figure 55 show simplified schematics of the ADC
in acquisition and conversion phase, respectively. The ADC
comprises control logic, a SAR, and two capacitive DACs. In
Figure 54 (the acquisition phase), SW3 is closed and SW1 and
SW2 are in Position A. The comparator is held in a balanced
condition, and the sampling capacitor arrays acquire the
differential signal on the input.
Internal reference (self-diagnostic feature).
Others Reserved.
CAPACITIVE
DAC
COMPARATOR
Table 23. ADCSTA Register
C
C
B
A
S
S
CHANNEL+
CHANNEL–
AIN0
Name
Address
Default Value
Access
SW1
SW2
CONTROL
LOGIC
MUX
SW3
ADCSTA
0xFFFF050C
0x00
R
A
B
AIN11
ADCSTA is an ADC status register that indicates when an ADC
conversion result is ready. The ADCSTA register contains only
one bit, ADCReady (Bit 0), representing the status of the ADC.
This bit is set at the end of an ADC conversion, generating an
ADC interrupt. It is cleared automatically by reading the
ADCDAT MMR. When the ADC is performing a conversion,
the status of the ADC can be read externally via the ADCBUSY
pin. This pin is high during a conversion. When the conversion
is finished, ADCBUSY goes back low. This information can be
available on P0.5 (see the General-Purpose Input/Output
section) if enabled in the ADCCON register.
V
REF
CAPACITIVE
DAC
Figure 54. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 55, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. The output
impedances of the sources driving the VIN+ and VIN– input
voltage pins must be matched; otherwise, the two inputs have
different settling times, resulting in errors.
Table 24. ADCDAT Register
Name
Address
Default Value
Access
ADCDAT
0xFFFF0510
0x00000000
R
ADCDAT is an ADC data result register. It holds the 12-bit
ADC result as shown in Figure 51.
CAPACITIVE
DAC
Table 25. ADCRST Register
Name
Address
Default Value
Access
COMPARATOR
C
C
B
A
S
S
CHANNEL+
CHANNEL–
AIN0
ADCRST
0xFFFF0514
0x00
R/W
SW1
SW2
CONTROL
LOGIC
MUX
SW3
ADCRST resets the digital interface of the ADC. Writing any value
to this register resets all the ADC registers to their default values.
A
B
AIN11
V
REF
Table 26. ADCGN Register
CAPACITIVE
DAC
Name
Address
Default Value
Access
Figure 55. ADC Conversion Phase
ADCGN
0xFFFF0530
0x0200
R/W
ADCGN is a 10-bit gain calibration register.
Rev. F | Page 48 of 104
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