Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Table 18. ADCCON MMR Bit Designations
Table 19. ADCCP Register
Bit
Value Description
Name
Address
Default Value
Access
15:13
12:10
Reserved.
ADC clock speed.
ADCCP
0xFFFF0504
0x00
R/W
ADCCP is an ADC positive channel selection register. This
MMR is described in Table 20.
000
fADC/1. This divider is provided to obtain
1 MSPS ADC with an external clock <41.78 MHz.
001
010
011
100
101
fADC/2 (default value).
fADC/4.
fADC/8.
fADC/16.
fADC/32.
ADC acquisition time.
Two clocks.
Four clocks.
Eight clocks (default value).
16 clocks.
Enable start conversion.
Table 20. ADCCP1 MMR Bit Designation
Bit
7:5
4:0
Value
Description
Reserved.
Positive channel selection bits.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
ADC0.
ADC1.
ADC2.
ADC3.
ADC4.
ADC5.
ADC6.
ADC7.
ADC8.
ADC9.
ADC10.
ADC11.
DAC0/ADC12.
DAC1/ADC13.
DAC2/ADC14.
DAC3/ADC15.
9:8
7
00
01
10
11
Set by the user to start any type of conversion
command. Cleared by the user to disable a
start conversion (clearing this bit does not
stop the ADC when continuously converting).
6
5
Reserved.
ADC power control.
Set by the user to place the ADC in normal
mode (the ADC must be powered up for at least
5 μs before it converts correctly). Cleared by the
user to place the ADC in power-down mode.
Conversion mode.
Single-ended mode.
Differential mode.
Pseudo differential mode.
Reserved.
Temperature sensor.
AGND (self-diagnostic feature).
Internal reference (self-diagnostic feature).
AVDD/2.
4:3
2:0
00
01
10
11
Others Reserved.
1 ADC and DAC channel availability depends on the part model. See Ordering
Guide for details.
Conversion type.
000
001
010
011
Enable CONVSTART pin as a conversion input.
Enable Timer1 as a conversion input.
Enable Timer0 as a conversion input.
Single software conversion. Sets to 000 after
conversion (note that Bit 7 of ADCCON MMR
should be cleared after starting a single
software conversion to avoid further
Table 21. ADCCN Register
Name
Address
Default Value
Access
ADCCN
0xFFFF0508
0x01
R/W
ADCCN is an ADC negative channel selection register. This
MMR is described in Table 22.
conversions triggered by the CONVSTART pin).
100
101
Continuous software conversion.
PLA conversion.
Other Reserved.
Rev. F | Page 47 of 104
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