欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
 浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第37页浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第38页浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第39页浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第40页浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第42页浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第43页浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第44页浏览型号ADuC7020BCPZ62I-RL的Datasheet PDF文件第45页  
Data Sheet  
ADuC7019/20/21/22/24/25/26/27/28/29  
MEMORY ORGANIZATION  
The ADuC7019/20/21/22/24/25/26/27/28/29 incorporate two  
separate blocks of memory: 8 kB of SRAM and 64 kB of on-chip  
Flash/EE memory. The 62 kB of on-chip Flash/EE memory is  
available to the user, and the remaining 2 kB are reserved for  
the factory-configured boot page. These two blocks are mapped  
as shown in Figure 45.  
FLASH/EE MEMORY  
The total 64 kB of Flash/EE memory is organized as 32 k × 16 bits;  
31 k × 16 bits is user space and 1 k × 16 bits is reserved for the  
on-chip kernel. The page size of this Flash/EE memory is 512 bytes.  
Sixty-two kilobytes of Flash/EE memory are available to the  
user as code and nonvolatile data memory. There is no  
distinction between data and program because ARM code  
shares the same space. The real width of the Flash/EE memory  
is 16 bits, which means that in ARM mode (32-bit instruction),  
two accesses to the Flash/EE are necessary for each instruction  
fetch. It is therefore recommended to use thumb mode when  
executing from Flash/EE memory for optimum access speed.  
The maximum access speed for the Flash/EE memory is  
41.78 MHz in thumb mode and 20.89 MHz in full ARM mode.  
More details about Flash/EE access time are outlined in the  
Execution Time from SRAM and Flash/EE section.  
0xFFFFFFFF  
0xFFFF0000  
MMRs  
RESERVED  
0x40000FFFF  
EXTERNAL MEMORY REGION 3  
0x40000000  
RESERVED  
0x30000FFFF  
EXTERNAL MEMORY REGION 2  
0x30000000  
RESERVED  
0x20000FFFF  
EXTERNAL MEMORY REGION 1  
0x20000000  
RESERVED  
0x10000FFFF  
EXTERNAL MEMORY REGION 0  
0x10000000  
RESERVED  
0x0008FFFF  
SRAM  
FLASH/EE  
0x00080000  
Eight kilobytes of SRAM are available to the user, organized as  
2 k × 32 bits, that is, two words. ARM code can run directly  
from SRAM at 41.78 MHz, given that the SRAM array is  
configured as a 32-bit wide memory array. More details about  
SRAM access time are outlined in the Execution Time from  
SRAM and Flash/EE section.  
RESERVED  
0x00011FFF  
SRAM  
0x00010000  
0x0000FFFF REMAPPABLE MEMORY SPACE  
0x00000000  
(FLASH/EE OR SRAM)  
Figure 45. Physical Memory Map  
Note that by default, after a reset, the Flash/EE memory is  
mirrored at Address 0x00000000. It is possible to remap the  
SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP  
MMR. This remap function is described in more detail in the  
Flash/EE Memory section.  
MEMORY MAPPED REGISTERS  
The memory mapped register (MMR) space is mapped into the  
upper two pages of the memory array and accessed by indirect  
addressing through the ARM7 banked registers.  
MEMORY ACCESS  
The MMR space provides an interface between the CPU and all  
on-chip peripherals. All registers, except the core registers, reside  
in the MMR area. All shaded locations shown in Figure 47 are  
unoccupied or reserved locations and should not be accessed by  
user software. Table 16 shows the full MMR memory map.  
The ARM7 core sees memory as a linear array of a 232 byte  
location where the different blocks of memory are mapped as  
outlined in Figure 45.  
The ADuC7019/20/21/22/24/25/26/27/28/29 memory organiza-  
tions are configured in little endian format, which means that  
the least significant byte is located in the lowest byte address,  
and the most significant byte is in the highest byte address.  
The access time for reading from or writing to an MMR  
depends on the advanced microcontroller bus architecture  
(AMBA) bus used to access the peripheral. The processor has  
two AMBA buses: the advanced high performance bus (AHB)  
used for system modules and the advanced peripheral bus  
(APB) used for lower performance peripheral. Access to the  
AHB is one cycle, and access to the APB is two cycles. All  
peripherals on the ADuC7019/20/21/22/24/25/26/27/28/29 are  
on the APB except the Flash/EE memory, the GPIOs (see  
Table 78), and the PWM.  
BIT 31  
BIT 0  
BYTE 3 BYTE 2 BYTE 1 BYTE 0  
.
.
.
.
.
.
.
.
.
.
.
.
0xFFFFFFFF  
B
7
3
A
6
2
9
5
1
8
4
0
0x00000004  
0x00000000  
32 BITS  
Figure 46. Little Endian Format  
Rev. F | Page 41 of 104