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ADuC7020BCPZ62I-RL 参数 Datasheet PDF下载

ADuC7020BCPZ62I-RL图片预览
型号: ADuC7020BCPZ62I-RL
PDF下载: 下载PDF文件 查看货源
内容描述: 精密模拟微控制器, 12位模拟I / O , ARM7TDMI MCU [Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 104 页 / 1747 K
品牌: ADI [ ADI ]
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Data Sheet  
ADuC7019/20/21/22/24/25/26/27/28/29  
AV  
DD  
Pseudo Differential Mode  
In pseudo differential mode, Channel− is linked to the VIN− pin  
of the ADuC7019/20/21/22/24/25/26/27/28/29. SW2 switches  
between A (Channel−) and B (VREF). The VIN− pin must be  
connected to ground or a low voltage. The input signal on VIN+  
can then vary from VIN− to VREF + VIN−. Note that VIN− must be  
chosen so that VREF + VIN− does not exceed AVDD.  
D
C2  
R1  
C1  
D
AV  
DD  
D
D
C2  
R1  
CAPACITIVE  
DAC  
C1  
COMPARATOR  
C
C
B
A
S
S
CHANNEL+  
AIN0  
SW1  
SW2  
CONTROL  
LOGIC  
MUX  
SW3  
Figure 58. Equivalent Analog Input Circuit Conversion Phase: Switches Open,  
Track Phase: Switches Closed  
A
B
AIN11  
V
For ac applications, removing high frequency components from  
the analog input signal is recommended by using an RC low-  
pass filter on the relevant analog input pins. In applications  
where harmonic distortion and signal-to-noise ratio are critical,  
the analog input should be driven from a low impedance  
source. Large source impedances significantly affect the ac  
performance of the ADC. This can necessitate the use of an  
input buffer amplifier. The choice of the op amp is a function of  
the particular application. Figure 59 and Figure 60 give an  
example of an ADC front end.  
REF  
CAPACITIVE  
DAC  
V
IN–  
CHANNEL–  
Figure 56. ADC in Pseudo Differential Mode  
Single-Ended Mode  
In single-ended mode, SW2 is always connected internally to  
ground. The VIN− pin can be floating. The input signal range on  
VIN+ is 0 V to VREF.  
CAPACITIVE  
DAC  
COMPARATOR  
C
C
B
A
S
S
CHANNEL+  
AIN0  
ADuC7019/  
ADuC702x  
SW1  
CONTROL  
LOGIC  
MUX  
SW3  
10  
ADC0  
CHANNEL–  
AIN11  
0.01µF  
CAPACITIVE  
DAC  
Figure 59. Buffering Single-Ended/Pseudo Differential Input  
Figure 57. ADC in Single-Ended Mode  
ADuC7019/  
ADuC702x  
Analog Input Structure  
ADC0  
V
REF  
Figure 58 shows the equivalent circuit of the analog input structure  
of the ADC. The four diodes provide ESD protection for the analog  
inputs. Care must be taken to ensure that the analog input  
signals never exceed the supply rails by more than 300 mV;  
exceeding 300 mV causes these diodes to become forward-  
biased and start conducting into the substrate. These diodes can  
conduct up to 10 mA without causing irreversible damage to  
the part.  
ADC1  
Figure 60. Buffering Differential Inputs  
When no amplifier is used to drive the analog input, the source  
impedance should be limited to values lower than 1 kΩ. The  
maximum source impedance depends on the amount of total  
harmonic distortion (THD) that can be tolerated. The THD  
increases as the source impedance increases and the performance  
degrades.  
The C1 capacitors in Figure 58 are typically 4 pF and can be  
primarily attributed to pin capacitance. The resistors are  
lumped components made up of the on resistance of the  
switches. The value of these resistors is typically about 100 Ω.  
The C2 capacitors are the ADC’s sampling capacitors and  
typically have a capacitance of 16 pF.  
DRIVING THE ANALOG INPUTS  
Internal or external references can be used for the ADC. In  
the differential mode of operation, there are restrictions on the  
common-mode input signal (VCM), which is dependent upon  
the reference value and supply voltage used to ensure that the  
signal remains within the supply rails. Table 28 gives some  
calculated VCM minimum and VCM maximum values.  
Rev. F | Page 49 of 104