ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ACQ
BIT TRIAL
WRITE
TYPICAL OPERATION
Once configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
ADC CLOCK
CONV
START
The top four bits are the sign bits. The 12-bit result is placed
from Bit 16 to Bit 27, as shown in Figure 51. Again, it should be
noted that, in fully differential mode, the result is represented in
twos complement format. In pseudo differential and single-
ended modes, the result is represented in straight binary format.
ADC
BUSY
DATA
ADCDAT
31
27
16 15
0
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
SIGN BITS
12-BIT ADC RESULT
Figure 51. ADC Result Format
Figure 52. ADC Timing
The same format is used in DACxDAT, simplifying the software.
ADuC7019
Current Consumption
The ADuC7019 is identical to the ADuC7020 except for one
buffered ADC channel, ADC3, and it has only three DACs. The
output buffer of the fourth DAC is internally connected to the
ADC3 channel as shown in Figure 53.
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA
multiplied by the sampling frequency (in kilohertz (kHz)).
Figure 43 shows the current consumption vs. the sampling
frequency of the ADC.
ADuC7019
1MSPS
12-BIT ADC
12-BIT
DAC
MUX
Timing
ADC3
DAC3
Figure 52 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight clocks
and the clock divider is 2. The number of extra clocks (such as
bit trial or write) is set to 19, which gives a sampling rate of
774 kSPS. For conversion on the temperature sensor, the ADC
acquisition time is automatically set to 16 clocks, and the ADC
clock divider is set to 32. When using multiple channels,
including the temperature sensor, the timing settings revert to
the user-defined settings after reading the temperature sensor
channel.
ADC15
Figure 53. ADC3 Buffered Input
Note that the DAC3 output pin must be connected to a 10 nF
capacitor to AGND. This channel should be used to measure dc
voltages only. ADC calibration may be necessary on this channel.
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
Table 17. ADCCON Register
Name
Address
Default Value
Access
ADCCON
0xFFFF0500
0x0600
R/W
ADCCON is an ADC control register that allows the programmer
to enable the ADC peripheral, select the mode of operation of
the ADC (in single-ended mode, pseudo differential mode, or
fully differential mode), and select the conversion type. This
MMR is described in Table 18.
Rev. F | Page 46 of 104
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