ADSP-BF561
SPECIFICATIONS
Component specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter
V
DDINT
Internal Supply Voltage
1
V
DDINT
Internal Supply Voltage
3
V
DDINT
Internal Supply Voltage
V
DDEXT
External Supply Voltage
V
DDEXT
External Supply Voltage
V
IH
High Level Input Voltage
4, 5
V
IL
Low Level Input Voltage
T
J
Junction Temperature
T
J
Junction Temperature
T
J
Junction Temperature
T
J
Junction Temperature
T
J
Junction Temperature
1
2
Conditions
Non automotive 500 MHz and 533 MHz speed grade models
2
600 MHz speed grade models
Automotive grade models
Non automotive grade models
Automotive grade models
Min
0.8
0.8
0.95
2.25
2.7
2.0
–0.3
256-Ball CSP_BGA (12 mm
×
12 mm) @ T
AMBIENT
= 0°C to +70°C
0
256-Ball CSP_BGA (17 mm
×
17 mm) @ T
AMBIENT
= 0°C to +70°C
0
256-Ball CSP_BGA (17 mm
×
17 mm) @ T
AMBIENT
=–40°C to +85°C –40
297-Ball PBGA @ T
AMBIENT
= 0°C to +70°C
0
297-Ball PBGA @ T
AMBIENT
= –40°C to +85°C
–40
Nominal
1.25
1.35
1.25
2.5, or 3.3
3.3
Max
1.375
1.4185
1.375
3.6
3.6
3.6
+0.6
+105
+95
+115
+95
+115
Unit
V
V
V
V
V
V
V
°C
°C
°C
°C
°C
Internal voltage (V
DDINT
) regulator tolerance is –5% to +10% for all models.
See
3
The internal voltage regulation feature is not available. External voltage regulation is required to ensure correct operation.
4
The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum V
IH
), but voltage compliance (on outputs, V
OH
) depends on the input V
DDEXT
, because V
OH
(maximum)
approximately equals V
DDEXT
(maximum). This 3.3 V tolerance applies to bidirectional and input only pins.
5
Applies to all signal pins.
and
describe the timing requirements for the
ADSP-BF561 clocks (t
CCLK
= 1/f
CCLK
). Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock, system clock, and Voltage Controlled Oscillator
(VCO) operating frequencies, as described in
describes phase-locked loop
operating conditions.
Table 9. Core Clock (CCLK) Requirements—500 MHz and 533 MHz Speed Grade Models
1
Parameter
f
CCLK
CCLK Frequency (V
DDINT
= 1.235 Vminimum)
2
CCLK Frequency (V
DDINT
= 1.1875 Vminimum)
f
CCLK
f
CCLK
CCLK Frequency (V
DDINT
= 1.045 Vminimum)
CCLK Frequency (V
DDINT
= 0.95 Vminimum)
f
CCLK
f
CCLK
CCLK Frequency (V
DDINT
= 0.855 Vminimum)
3
f
CCLK
CCLK Frequency (V
DDINT
= 0.8 V minimum)
1
2
Max
533
500
444
350
300
250
Unit
MHz
MHz
MHz
MHz
MHz
MHz
See
External Voltage regulation is required on automotive grade models (see
to ensure correct operation.
3
Not applicable to automotive grade models. See
Table 10. Core Clock (CCLK) Requirements—600 MHz Speed Grade Models
1
Parameter
CCLK Frequency (V
DDINT
= 1.2825 V minimum)
2
f
CCLK
f
CCLK
CCLK Frequency (V
DDINT
= 1.235 V minimum)
f
CCLK
CCLK Frequency (V
DDINT
= 1.1875 V minimum)
f
CCLK
CCLK Frequency (V
DDINT
= 1.045 V minimum)
CCLK Frequency (V
DDINT
= 0.95 V minimum)
f
CCLK
f
CCLK
CCLK Frequency (V
DDINT
= 0.855 V minimum)
CCLK Frequency (V
DDINT
= 0.8 V minimum)
f
CCLK
1
2
Max
600
533
500
444
350
300
250
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
See
External voltage regulator required to ensure proper operation at 600 MHz.
Rev. E |
Page 20 of 64 |
September 2009
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