ADSP-BF561SBB500 参数 Datasheet PDF下载

ADSP-BF561

Table 8. Pin Descriptions (Continued)

Pin Name

SPORT1

RSCLK1/PF30

RFS1/PF24

DR1PRI

DR1SEC/PF25

TSCLK1/PF31

TFS1/PF21

DT1PRI/PF23

DT1SEC/PF22

SPI

MOSI

MISO

SCK

UART

RX/PF27

TX/PF26

JTAG

EMU

TCK

TDO

TDI

TMS

TRST

Clock

CLKIN

XTAL

Mode Controls

RESET

NMI0

NMI1

BMODE1–0

SLEEP

BYPASS

Voltage Regulator

V

ROUT

1–0

Supplies

V

DDEXT

V

DDINT

GND

No Connection

1

Type Function

I/O

I/O

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

I

O

I

I

I

I

O

I

I

I

I

O

I

O

P

P

G

NC

Sport1 Receive Serial Clock/Programmable

Flag

Sport1 Receive Frame Sync/Programmable

Flag

Sport1 Receive Data Primary

Sport1 Receive Data Secondary/Programmable

Flag

Sport1 Transmit Serial Clock/Programmable

Flag

Sport1 Transmit Frame Sync/Programmable

Flag

Sport1 Transmit Data Primary/Programmable

Flag

Sport1 Transmit Data Secondary/Programmable

Flag

Master Out Slave In

Master In Slave Out (This pin should be pulled HIGH through a 4.7 kΩ resistor if booting via the SPI

port.)

SPI Clock

UART Receive/Programmable

Flag

UART Transmit/Programmable

Flag

Emulation Output

JTAG Clock

JTAG Serial Data Out

JTAG Serial Data In

JTAG Mode Select

JTAG Reset (This pin should be pulled LOW if JTAG is not used.)

Clock/Crystal Input (This pin needs to be at a level or clocking.)

Crystal Connection

Reset (This pin is always active during core power-on.)

Nonmaskable Interrupt Core A (This pin should be pulled LOW when not used.)

Nonmaskable Interrupt Core B (This pin should be pulled LOW when not used.)

Boot Mode Strap (These pins must be pulled to the state required for the desired boot mode.)

Sleep

PLL BYPASS Control (Pull-up or pull-down Required.)

External FET Drive

Power Supply

Power Supply

Power Supply Return

NC

Driver

Type

1

D

C

C

D

C

C

C

C

C

D

C

C

C

C

C

Refer to

to

Rev. E |

Page 19 of 64 |

September 2009