ADSP-BF561
TIMING SPECIFICATIONS
Clock and Reset Timing
and
describe clock and reset operations. Per
combinations of
CLKIN and clock multipliers must not result in core/system
clocks exceeding the maximum limits allowed for the processor,
including system clock restrictions related to supply voltage.
Table 16. Clock and Normal Reset Timing
Parameter
Timing Requirements
t
CKIN
CLKIN (to PLL) Period
1, 2, 3
t
CKINL
CLKIN Low Pulse
t
CKINH
CLKIN High Pulse
t
WRST
RESET Asserted Pulse Width Low
4
1
2
Min
25.0
10.0
10.0
11
×
t
CKIN
Max
100.0
Unit
ns
ns
ns
ns
If DF bit in PLL_CTL register is set t
CLKIN
is divided by two before going to PLL, then the t
CLKIN
maximum period is 50 ns and the t
CLKIN
minimum period is 12.5 ns.
Applies to PLL bypass mode and PLL nonbypass mode.
3
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in
through
4
Applies after power-up sequence is complete. See
and
for power-up reset timing.
t
CKIN
CLKIN
t
CKINL
RESET
t
CKINH
t
WRST
Figure 8. Clock and Normal Reset Timing
Table 17. Power-Up Reset Timing
Parameter
Timing Requirements
t
RST
_
IN
_
PWR
RESET Deasserted after the V
DDINT
, V
DDEXT
, and CLKIN Pins are Stable and Within
Specification
t
RST_IN_PWR
RESET
Min
3500
×
t
CKIN
Max
Unit
μs
CLKIN,
V
DDINT,
V
DDEXT
Figure 9. Power-Up Reset Timing
Rev. E |
Page 23 of 64 |
September 2009
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