ADSP-BF561
PIN DESCRIPTIONS
ADSP-BF561 pin definitions are listed in
In order to
maintain maximum function and reduce package size and pin
count, some pins have multiple functions. In cases where pin
function is reconfigurable, the default state is shown in plain
text, while alternate functionality is shown in italics.
All pins are three-stated during and immediately after reset,
except the external memory interface, asynchronous memory
control, and synchronous memory control pins. These pins are
Table 8. Pin Descriptions
Pin Name
EBIU
ADDR25–2
DATA31–0
ABE3–0/SDQM3–0
BR
BG
BGH
EBIU (ASYNC)
AMS3–0
ARDY
AOE
AWE
ARE
EBIU (SDRAM)
SRAS
SCAS
SWE
SCKE
SCLK0/CLKOUT
SCLK1
SA10
SMS3–0
Type Function
O
I/O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
Address Bus for Async/Sync Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access
Bus Request (This pin should be pulled HIGH if not used.)
Bus Grant
Bus Grant Hang
Bank Select
Hardware Ready Control (This pin should be pulled HIGH if not used.)
Output Enable
Write Enable
Read Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output Pin 0
Clock Output Pin 1
SDRAM A10 Pin
Bank Select
Driver
Type
1
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
A
A
all driven high, with the exception of CLKOUT, which toggles at
the system clock rate. However if BR is active, the memory pins
are also three-stated.
All I/O pins have their input buffers disabled, with the exception
of the pins that need pull-ups or pull-downs if unused, as noted
in
Rev. E |
Page 17 of 64 |
September 2009
AD [ ANALOG DEVICES ]
