ADSP-BF561
Table 11. Phase-Locked Loop Operating Conditions
Parameter
Voltage Controlled Oscillator (VCO) Frequency
Min
50
Max
Maximum f
CCLK
Unit
MHz
Table 12. System Clock (SCLK) Requirements
Parameter
1
f
SCLK
f
SCLK
1
2
CLKOUT/SCLK Frequency (V
DDINT
≥
1.14 V)
CLKOUT/SCLK Frequency (V
DDINT
<
1.14 V)
Max V
DDEXT
= 2.5V/3.3V
133
2
100
Unit
MHz
MHz
t
SCLK
(= 1/f
SCLK
) must be greater than or equal to t
CCLK
.
Rounded number. Guaranteed to t
SCLK
= 7.5 ns. See
ELECTRICAL CHARACTERISTICS
Parameter
V
OH
V
OL
I
IH
I
IHP
I
IL
4
I
OZH
I
OZL
C
IN
I
DDHIBERNATE
8
I
DDDEEPSLEEP
9
I
DD
_
TYP
I
DD
_
TYP
I
DD
_
TYP
1
2
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
2
High Level Input Current JTAG
3
Low Level Input Current
Three-State Leakage Current
5
Three-State Leakage Current
Input Capacitance
6
V
DDEXT
Current in Hibernate Mode
V
DDINT
Current in Deep Sleep Mode
V
DDINT
Current
V
DDINT
Current
V
DDINT
Current
1
Test Conditions
Min
V
DDEXT
= 3.0 V, I
OH
= –0.5 mA
2.4
V
DDEXT
= 3.0 V, I
OL
= 2.0 mA
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum
V
DDEXT
= Maximum, V
IN
= 0 V
V
DDEXT
= Maximum, V
IN
= V
DD
Maximum
V
DDEXT
= Maximum, V
IN
= 0 V
f
IN
= 1 MHz, T
AMBIENT
= 25°C, V
IN
= 2.5 V
CLKIN=0 MHz, V
DDEXT
= 3.65 V with Voltage Regulator Off
(V
DDINT
= 0 V)
V
DDINT
= 0.8 V, T
JUNCTION
= 25°C
V
DDINT
= 0.8 V, f
CCLK
= 50 MHz, T
JUNCTION
= 25°C
V
DDINT
= 1.25 V, f
CCLK
= 500 MHz, T
JUNCTION
= 25°C
V
DDINT
= 1.35 V, f
CCLK
= 600 MHz, T
JUNCTION
= 25°C
Typical
Max
0.4
10.0
50.0
10.0
10.0
10.0
8
7
4
50
70
127
660
818
Unit
V
V
μA
μA
μA
μA
μA
pF
μA
mA
mA
mA
mA
Applies to output and bidirectional pins.
Applies to input pins except JTAG inputs.
3
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
4
Absolute value.
5
Applies to three-statable pins.
6
Applies to all signal pins.
7
Guaranteed, but not tested.
8
CLKIN must be tied to V
DDEXT
or GND during hibernate.
9
Maximum current drawn. See
Estimating Power for ADSP-BF561 Blackfin Processors (EE-293)
on the Analog Devices website (www.analog.com)—use site search on “EE-293”.
10
Both cores executing 75% dual MAC, 25% ADD instructions with moderate data bus activity.
System designers should refer to
Estimating Power for the
ADSP-BF561 (EE-293),
which provides detailed information for
optimizing designs for lowest power. All topics discussed in this
section are described in detail in EE-293. Total power dissipa
tion has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro
cessor activity.
shows the
current dissipation for internal circuitry (V
DDINT
).
Rev. E |
Page 21 of 64 |
September 2009
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