ADSP-BF561
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the
ADSP-BF561 processors as possible.
For further details on the on-chip voltage regulator and related
board design guidelines, see the
Switching Regulator Design
Considerations for ADSP-BF533 Blackfin Processors (EE-228)
applications note on the Analog Devices web site (www.ana
site search on “EE-228”.
Blackfin
CLKOUT
TO PLL CIRCUITRY
EN
700O
V
DDEXT
CLKIN
XTAL
0O*
1MO
CLOCK SIGNALS
The ADSP-BF561 processor can be clocked by an external crys
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF561 processor includes an
on-chip oscillator circuit, an external crystal may be used. For
fundamental frequency operation, use the circuit shown in
A parallel-resonant, fundamental frequency, micro
processor-grade crystal is connected across the CLKIN and
XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Further parallel resistors are
typically not recommended. The two capacitors and the series
resistor shown in
fine tune the phase and amplitude of
the sine frequency. The capacitor and resistor values shown in
are typical values only. The capacitor values are depen
dent upon the crystal manufacturer’s load capacitance
recommendations and the physical PCB layout. The resistor
value depends on the drive level specified by the crystal manu
facturer. System designs should verify the customized values
based on careful investigation on multiple devices over the
allowed temperature range.
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in
As shown in
the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user-programmable 0.5× to 64× multiplica
tion factor. The default multiplier is 10×, but it can be modified
by a software instruction sequence. On the fly frequency
changes can be effected by simply writing to the PLL_DIV
register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
18pF*
18pF*
FOR OVERTONE
OPERATION ONLY
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure 5. External Crystal Connections
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
÷ 1, 2, 4, 8
CLKIN
PLL
0.5u to 64u
CCLK
VCO
÷ 1 to 15
SCLK
SCLK
d
CCLK
SCLK
d
133 MHz
Figure 6. Frequency Modification Methods
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
illustrates typical system clock ratios.
Table 5. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0110
1010
Divider Ratio
VCO/SCLK
1:1
6:1
10:1
Example Frequency
Ratios (MHz)
VCO
SCLK
100
100
300
50
500
50
The maximum frequency of the system clock is f
SCLK
. Note that
the divisor ratio must be chosen to limit the system clock fre
quency to its maximum of f
SCLK
. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
Rev. E |
Page 13 of 64 |
September 2009
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