ADSP-BF561
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt
age (V
DDINT
) to 0 V to provide the lowest static power dissipation.
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a nonvolatile storage
device prior to removing power if the processor state is to be
preserved. Since V
DDEXT
is still supplied in this mode, all of the
external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up by asserting the
RESET pin.
t
NOM
is the duration running at
f
CCLKNOM
t
RED
is the duration running at
f
CCLKRED
The percent power savings is calculated as:
% power savings
=
(1
–
power savings factor)
×
100%
VOLTAGE REGULATION
The ADSP-BF561 processor provides an on-chip voltage regula
tor that can generate appropriate V
DDINT
voltage levels from the
V
DDEXT
supply. See
for regula
tor tolerances and acceptable V
DDEXT
ranges for specific models.
shows the typical external components required to
complete the power management system. The regulator con
trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while keeping I/O power (V
DDEXT
) supplied. While
in the hibernate state, V
DDEXT
can still be applied, thus eliminating
the need for external buffers. The voltage regulator can be acti
vated from this power-down state by asserting RESET, which
will then initiate a boot sequence. The regulator can also be dis
abled and bypassed at the user’s discretion.
The internal voltage regulation feature is not available on any of
the 600 MHz speed grade models or automotive grade models.
External voltage regulation is required to ensure correct opera
tion of these parts at 600 MHz.
Power Savings
As shown in
the ADSP-BF561 supports two different
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan
dards and conventions. By isolating the internal logic of the
ADSP-BF561 into its own power domain, separate from the I/O,
the processor can take advantage of Dynamic Power Manage
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.
Table 4. ADSP-BF561 Power Domains
Power Domain
All internal logic
I/O
V
DD
Range
V
DDINT
V
DDEXT
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The dynamic power management feature of the ADSP-BF561
allows both the processor’s input voltage (V
DDINT
) and clock fre-
quency (f
CCLK
) to be dynamically controlled.
The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.
The power savings factor is calculated as:
power savings factor
f
CCLKRED
V
DDINTRED 2
t
RED
-
-
-
= --------------------
×
-------------------------
×
----------
f
CCLKNOM
V
DDINTNOM
t
NOM
where the variables in the equations are:
f
CCLKNOM
is the nominal core clock frequency
f
CCLKRED
is the reduced core clock frequency
V
DDINTNOM
is the nominal internal supply voltage
V
DDINTRED
is the reduced internal supply voltage
V
DDEXT
(LOW-INDUCTANCE)
SET OF DECOUPLING
CAPACITORS
V
DDEXT
+
100μF
100nF
+
100μF
FDS9431A
10μF
LOW ESR
100μF
ZHCS1000
10μH
+
V
DDINT
VR
OUT
SHORT AND LOW-
INDUCTANCE WIRE
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
VR
OUT
GND
Figure 4. Voltage Regulator Circuit
Voltage Regulator Layout Guidelines
Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1–0 traces
and voltage regulator external components should be consid
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
Rev. E |
Page 12 of 64 |
September 2009
AD [ ANALOG DEVICES ]
