ADSP-BF561
even though the event may be latched in the ILAT register.
This register may be read from or written to while in
supervisor mode.
Note that general-purpose interrupts can be globally
enabled and disabled with the STI and CLI instructions,
respectively.
• CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
six 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in
• SIC Interrupt Mask Registers (SIC_IMASKx) – These reg
isters control the masking and unmasking of each
peripheral interrupt event. When a bit is set in these regis
ters, that peripheral event is unmasked and will be
processed by the system when asserted. A cleared bit in
these registers masks the peripheral event, thereby prevent
ing the processor from servicing the event.
• SIC Interrupt Status Registers (SIC_ISRx) – As multiple
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt; a cleared bit indicates
the peripheral is not asserting the event.
• SIC Interrupt Wakeup Enable Registers (SIC_IWRx) – By
enabling the corresponding bit in these registers, each
peripheral can be configured to wake up the processor,
should the processor be in a powered-down mode when
the event is generated.
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend
ing on the activity within and the mode of the processor.
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interfaces, including
the SDRAM controller and the asynchronous memory
controller. DMA-capable peripherals include the SPORTs, SPI
port, UART, and PPIs. Each individual DMA-capable periph
eral has at least one dedicated DMA channel.
The ADSP-BF561 DMA controllers support both 1-dimen
sional (1-D) and 2-dimensional (2-D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to
±
32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the ADSP-BF561 DMA
controllers include:
• A single linear buffer that stops upon completion.
• A circular autorefreshing buffer that interrupts on each full
or fractionally full buffer.
• 1-D or 2-D DMA using a linked list of descriptors.
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page.
In addition to the dedicated peripheral DMA channels, each
DMA Controller has four memory DMA channels provided for
transfers between the various memories of the ADSP-BF561
system. These enable transfers of blocks of data between any of
the memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor-
based methodology or by a standard register-based autobuffer
mechanism.
Further, the ADSP-BF561 has a four channel Internal Memory
DMA (IMDMA) Controller. The IMDMA Controller allows
data transfers between any of the internal L1 and L2 memories.
WATCHDOG TIMER
Each ADSP-BF561 core includes a 32-bit timer, which can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces
sor to a known state, via generation of a hardware reset,
nonmaskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
DMA CONTROLLERS
The ADSP-BF561 has two independent DMA controllers that
support automated data transfers with minimal overhead for
the DSP cores. DMA transfers can occur between the
ADSP-BF561 internal memories and any of its DMA-capable
Rev. E |
Page 8 of 64 |
September 2009
AD [ ANALOG DEVICES ]
