ADSP-BF561
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
timer control register, which is set only upon a watchdog gener
ated reset.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of f
SCLK
.
• DMA operations with single-cycle overhead – Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The DSP can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts – Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability – Each SPORT supports 128 chan
nels out of a 1,024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
An additional 250 mV of SPORT input hysteresis can be
enabled by setting Bit 15 of the PLL_CTL register. When this bit
is set, all SPORT input pins have the increased hysteresis.
TIMERS
There are 14 programmable timer units in the ADSP-BF561.
Each of the 12 general-purpose timer units can be indepen
dently programmed as a Pulse Width Modulator (PWM),
internally or externally clocked timer, or pulse width counter.
The general-purpose timer units can be used in conjunction
with the UART to measure the width of the pulses in the data
stream to provide an autobaud detect function for a serial chan
nel. The general-purpose timers can generate interrupts to the
processor core providing periodic events for synchronization,
either to the processor clock or to a count of external signals.
In addition to the 12 general-purpose programmable timers,
another timer is also provided for each core. These extra timers
are clocked by the internal processor clock (CCLK) and are typ
ically used as a system tick clock for generation of operating
system periodic interrupts.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The ADSP-BF561 processor has an SPI-compatible port that
enables the processor to communicate with multiple SPI-com
patible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSI, and master input-slave
output, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the proces
sor, and seven SPI chip select output pins (SPISEL7–1) let the
processor select other SPI devices. The SPI select pins are recon
figured programmable flag pins. Using these pins, the SPI port
provides a full-duplex, synchronous serial interface which sup
ports both master/slave modes and multimaster environments.
The baud rate and clock phase/polarities for the SPI port are
programmable, and it has an integrated DMA controller, con
figurable to support transmit or receive data streams. The SPI
DMA controller can only service unidirectional accesses at any
given time.
The SPI port clock rate is calculated as:
f
SCLK
-
SPI Clock Rate
= -----------------------------------
2
×
SPI_BAUD
Where the 16-bit SPI_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam
pling of data on the two serial data lines.
SERIAL PORTS (SPORTs)
The ADSP-BF561 incorporates two dual-channel synchronous
serial ports (SPORT0 and SPORT1) for serial and multiproces
sor communications. The SPORTs support the following
features:
• I S capable operation.
• Bidirectional operation – Each SPORT has two sets of inde
pendent transmit and receive pins, enabling eight channels
of I
2
S stereo audio.
• Buffered (8-deep) transmit and receive ports – Each port
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.
• Clocking – Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (f
SCLK
/131,070) Hz to (f
SCLK
/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 bits to 32 bits in length, transferred most significant
bit first or least significant bit first.
• Framing – Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware – Each SPORT can perform
A-law or μ-law companding according to ITU recommen
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
2
UART PORT
The ADSP-BF561 processor provides a full-duplex universal
asynchronous receiver/transmitter (UART) port, which is fully
compatible with PC-standard UARTs. The UART port provides
a simplified UART interface to other peripherals or hosts, sup
porting full-duplex, DMA-supported, asynchronous transfers of
serial data. The UART port includes support for 5 data bits to
8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd par
ity. The UART port supports two modes of operation:
Rev. E |
Page 9 of 64 |
September 2009
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