ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 46 and Figure 39 describe SPI port slave operations.
Table 46. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
SPIxSCK High Period
2tSCLK –1.5
2tSCLK –1.5
4tSCLK
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSCK Low Period
SPIxSCK Period
Last SPIxSCK Edge to SPIxSS Not Asserted
Sequential Transfer Delay
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
tSPITDS
tSDSCI
tSSPID
tHSPID
SPIxSS Assertion to First SPIxSCK Edge
Data Input Valid to SPIxSCK Edge (Data Input Setup)
SPIxSCK Sampling Edge to Data Input Invalid
1.6
Switching Characteristics
tDSOE
SPIxSS Assertion to Data Out Active
0
0
8
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPIxSS Deassertion to Data High Impedance
SPIxSCK Edge to Data Out Valid (Data Out Delay)
SPIxSCK Edge to Data Out Invalid (Data Out Hold)
8
10
0
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
tHSPID
CPHA = 0
tSSPID
SPIxMOSI
(INPUT)
Figure 39. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. C
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Page 65 of 100
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February 2010
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