ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Serial Peripheral Interface (SPI) Port—Master Timing
Table 45 and Figure 38 describe SPI port master operations.
Table 45. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
tHSPIDM
Switching Characteristics
Data Input Valid to SPIxSCK Edge (Data Input Setup)
9.0
ns
ns
SPIxSCK Sampling Edge to Data Input Invalid
–1.5
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
SPIxSELy Low to First SPIxSCK Edge
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK–1.5
ns
ns
ns
ns
ns
ns
ns
ns
SPIxSCK High Period
SPIxSCK Low Period
SPIxSCK Period
tHDSM
Last SPIxSCK Edge to SPIxSELy High
Sequential Transfer Delay
tSPITDM
tDDSPIDM
tHDSPIDM
SPIxSCK Edge to Data Out Valid (Data Out Delay)
SPIxSCK Edge to Data Out Invalid (Data Out Hold)
6
–1.0
SPIxSELy
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
tSPITDM
SPIxSCK
(OUTPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
CPHA = 1
tHSPIDM
SPIxMISO
(INPUT)
tHDSPIDM
tDDSPIDM
SPIxMOSI
(OUTPUT)
tSSPIDM
tHSPIDM
CPHA = 0
SPIxMISO
(INPUT)
Figure 38. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. C
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Page 64 of 100
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February 2010
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