ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Serial Ports Timing
Table 41 through Table 44 on Page 63 and Figure 34 on Page 62
through Figure 37 on Page 63 describe serial port operations.
Table 41. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
3.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
Receive Data Setup Before RSCLKx1
Receive Data Hold After RSCLKx1
3.0
tSDRE
3.0
tHDRE
tSCLKEW
tSCLKE
tRCLKE
tSUDTE
tSUDRE
3.0
TSCLKx/RSCLKx Width
4.5
TSCLKx/RSCLKx Period
RSCLKx Period2
15.0
11.1
4 × tSCLKE
4 × tRCLKE
Start-Up Delay From SPORT Enable To First External TFSx
Start-Up Delay From SPORT Enable To First External RFSx
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)3
Transmit Data Delay After TSCLKx3
10.0
10.0
ns
ns
ns
ns
0.0
0.0
Transmit Data Hold After TSCLKx3
1 Referenced to sample edge.
2 For serial port receive with external clock and external frame sync only.
3 Referenced to drive edge.
Table 42. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
tHFSI
tSDRI
tHDRI
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
Receive Data Setup Before RSCLKx1
10.0
–1.5
10.0
–1.5
ns
ns
ns
ns
Receive Data Hold After RSCLKx1
Switching Characteristics
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
Transmit Data Delay After TSCLKx2
3.0
3.0
ns
ns
ns
ns
ns
tHOFSI
tDDTI
–1.0
tHDTI
Transmit Data Hold After TSCLKx2
–2.0
4.5
tSCLKIW
TSCLKx/RSCLKx Width
1 Referenced to sample edge.
2 Referenced to drive edge.
Rev. C
|
Page 61 of 100
|
February 2010
ADI [ ADI ]
