ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Synchronous Burst AC Timing
Table 38 and Figure 28 on Page 57 describe Synchronous Burst
AC operations.
Table 38. Synchronous Burst AC Timing
Parameter
Min
Max
Unit
Timing Requirements
tNDS
tNDH
tNWS
tNWH
DATA15-0 Setup Before NR_CLK
DATA15-0 Hold After NR_CLK
WAIT Setup Before NR_CLK
WAIT Hold After NR_CLK
4.0
2.0
8.0
0.0
ns
ns
ns
ns
Switching Characteristics
tNDO AMSx, ABE1-0, ADDR19-1, NR_ADV, NR_OE Output Delay After NR_CLK
tNHO
6.0
ns
ns
ABE1-0, ADDR19-1 Output Hold After NR_CLK
–3.0
NR_CLK
t
t
t
t
NDO
NDO
AMSx
NHO
NDO
NDO
ABE1-0
t
t
NHO
ADDR19-1
DATA15-0
t
t
NDH
NDH
t
t
NDS
NDS
Dn
Dn+1 Dn+2 Dn+3
t
NDO
t
NDO
NR_ADV
t
t
NWS
NWH
WAIT
t
NDO
t
NDO
NR_OE
NOTE: NR_CLK dotted line represents a free running version of NR_CLK that is not visible on the NR_CLK pin.
Figure 28. Synchronous Burst AC Interface Timing
Rev. C
|
Page 57 of 100
|
February 2010
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