ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Table 12. Pin Descriptions (Continued)
Driver
Type2
Pin Name
I/O1 Function (First/Second/Third/Fourth)
Port J: GPIO/AMC/ATAPI
PJ0 / ARDY/WAIT
PJ1 / ND_CE7
PJ2 / ND_RB
PJ3 / ATAPI_DIOR
PJ4 / ATAPI_DIOW
PJ5 / ATAPI_CS0
PJ6 / ATAPI_CS1
PJ7 / ATAPI_DMACK
PJ8 / ATAPI_DMARQ
PJ9 / ATAPI_INTRQ
PJ10 / ATAPI_IORDY
PJ11 / BR8
I/O GPIO/ Async Ready/NOR Wait
I/O GPIO/NAND Chip Enable
I/O GPIO/NAND Ready Busy
I/O GPIO/ATAPI Read
A
A
A
A
A
A
A
A
A
A
A
A
A
A
I/O GPIO/ATAPI Write
I/O GPIO/ATAPI Chip Select/Command Block
I/O GPIO/ATAPI Chip Select
I/O GPIO/ATAPI DMA Acknowledge
I/O GPIO/ATAPI DMA Request
I/O GPIO/Interrupt Request from the Device
I/O GPIO/ATAPI Ready Handshake
I/O GPIO/Bus Request
PJ12 / BG6
PJ13 / BGH6
I/O GPIO/Bus Grant
I/O GPIO/Bus Grant Hang
DDR Memory Interface
DA0–12
DBA0–1
DQ0–15
DQS0–1
DQM0–1
DCLK0–1
DCLK0–1
DCS0–1
DCLKE9
DRAS
DCAS
DWE
DDR_VREF
O
O
DDR Address Bus
DDR Bank Active Strobe
D
D
D
D
D
D
D
D
D
D
D
D
I/O DDR Data Bus
I/O DDR Data Strobe
O
O
O
O
O
O
O
O
I
DDR Data Mask for Reads and Writes
DDR Output Clock
DDR Complementary Output Clock
DDR Chip Selects
DDR Clock Enable
DDR Row Address Strobe
DDR Column Address Strobe
DDR Write Enable
DDR Voltage Reference
DDR_VSSR
I
DDR Voltage Reference Shield (Must be connected to GND.)
Asynchronous Memory Interface
A1-3
D0-15/ND_D0-15/ATAPI_D0-15
AMS0–3
O
Address Bus for Async and ATAPI Addresses
A
A
A
A
I/O Data Bus for Async, NAND and ATAPI Accesses
O
O
Bank Selects (Pull high with a resistor when used as chip select.)
Byte Enables:Data Masks for Asynchronous Access/NAND Command
ABE0 /ND_CLE
Latch Enable
ABE1/ND_ALE
O
Byte Enables:Data Masks for Asynchronous Access/NAND Address Latch A
Enable
AOE/NR_ADV
ARE
AWE
O
O
O
Output Enable/NOR Address Data Valid
Read Enable/NOR Output Enable
Write Enable
A
A
A
ATAPI Controller Pins
ATAPI_PDIAG
I
Determines if an 80-pin cable is connected to the host. (Pull high or low
when unused.)
Rev. C
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Page 31 of 100
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February 2010
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