ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
GENERAL DESCRIPTION
The ADSP-BF54x Blackfin® processors are members of the
Blackfin family of products, incorporating the Analog Devices/
Intel Micro Signal Architecture (MSA). Blackfin processors
combine a dual-MAC state-of-the-art signal processing engine,
the advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
Specific peripherals for ADSP-BF54x Blackfin processors are
shown in Table 2.
Table 2. Specific Peripherals for ADSP-BF54x Processors
Module
Specific performance, memory configurations, and features of
ADSP-BF54x Blackfin processors are shown in Table 1.
EBIU (async)
NAND flash controller
ATAPI
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
–
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
–
–
P
P
P
P
P
P
–
P
P
P
–
P
–
P
P
P
–
P
P
P
P
P
–
P
P
–
P
–
P
P
P
P
P
P
P
–
–
P
P
P
P
–
P
–
P
P
–
P
P
P
P
P
–
P
P
–
P
P
P
–
P
–
P
–
P
P
–
P
Table 1. ADSP-BF54x Processor Features
Processor
Features
Host DMA port (HOSTDP)
SD/SDIO controller
EPPI0
EPPI1
Lockbox® 1code security
128-bit AES/ ARC4 data encryption
SD/SDIO controller
Pixel compositor
18- or 24-bit EPPI0 with LCD
16-bit EPPI1, 8-bit EPPI2
Host DMA port
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
4
4
1
1
1
1
1
1
1
1
1
1
1
1
–
2
2
3
4
4
1
1
1
1
1
1
1
1
1
1
1
1
–
–
2
3
4
4
1
1
1
–
1
1
1
1
1
–
–
–
–
2
2
2
3
3
1
1
1
1
1
–
1
–
1
1
1
1
–
1
1
2
3
3
1
8
EPPI2
SPORT0
SPORT1
SPORT2
SPORT3
SPI0
SPI1
NAND flash controller
ATAPI
SPI2
UART0
High Speed USB OTG
Keypad interface
MXVR
UART1
UART2
UART3
CAN ports
High Speed USB OTG
CAN0
TWI ports
SPI ports
CAN1
UART ports
TWI0
SPORTs
TWI1
Up/Down counter
Timers
Timer 0–7
Timer 8–10
Up/Down counter
Keypad interface
MXVR
11 11 11 11
152 152 152 152 152
General-Purpose I/O pins
Memory
Configura-
tions
L1 Instruction SRAM/Cache 16 16 16 16 16
L1 Instruction SRAM
L1 Data SRAM/Cache
L1 Data SRAM
L1 Scratchpad SRAM
L1 ROM2
48 48 48 48 48
32 32 32 32 32
32 32 32 32 32
(K Bytes)
GPIOs
4
4
4
4
4
64 64 64 64 64
L2
128 128 128 64
–
4
L3 Boot ROM2
4
4
4
4
Maximum Core Instruction Rate (MHz) 533 533 600 533 600
1 Lockbox is a registered trademark of Analog Devices, Inc.
2 This ROM is not customer-configurable.
Rev. C
|
Page 3 of 100
|
February 2010
ADI [ ADI ]
