ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
TABLE OF CONTENTS
General Description ................................................. 3
Low Power Architecture ......................................... 4
System Integration ................................................ 4
Blackfin Processor Peripherals ................................. 4
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 6
DMA Controllers ................................................ 10
Real-Time Clock ................................................. 11
Watchdog Timer ................................................ 12
Timers ............................................................. 12
Up/Down Counter and Thumbwheel Interface .......... 12
Serial Ports (SPORTs) .......................................... 12
Serial Peripheral Interface (SPI) Ports ...................... 13
UART Ports (UARTs) .......................................... 13
Controller Area Network (CAN) ............................ 13
TWI Controller Interface ...................................... 14
Ports ................................................................ 14
Pixel Compositor (PIXC) ...................................... 14
Enhanced Parallel Peripheral Interface (EPPI) ........... 14
USB On-the-Go Dual-Role Device Controller ............ 15
ATA/ATAPI-6 Interface ....................................... 15
Keypad Interface ................................................. 15
Secure Digital (SD)/SDIO Controller ....................... 16
Code Security .................................................... 16
Media Transceiver MAC Layer (MXVR) .................. 16
Dynamic Power Management ................................ 16
Voltage Regulation .............................................. 18
Clock Signals ..................................................... 18
Booting Modes ................................................... 19
Instruction Set Description .................................... 22
Development Tools .............................................. 23
EZ-KIT Lite Evaluation Board ............................. 23
Designing an Emulator-Compatible Processor Board ... 23
MXVR Board Layout Guidelines ............................. 23
Related Documents .............................................. 24
Lockbox Secure Technology Disclaimer .................... 24
Pin Descriptions .................................................... 25
Specifications ........................................................ 34
Operating Conditions ........................................... 34
Electrical Characteristics ....................................... 36
Absolute Maximum Ratings ................................... 40
ESD Sensitivity ................................................... 41
Package Information ............................................ 41
Timing Specifications ........................................... 42
Output Drive Currents ......................................... 86
Test Conditions .................................................. 88
Capacitive Loading .............................................. 88
Typical Rise and Fall Times ................................... 89
Thermal Characteristics ........................................ 91
400-Ball CSP_BGA Package ...................................... 92
Outline Dimensions ................................................ 98
Surface-Mount Design .......................................... 98
Automotive Products .............................................. 99
Ordering Guide ................................................... 100
REVISION HISTORY
2/10—Rev. B to Rev. C
Added VIHTWI and VILTWI data to Operating Conditions ...... 34
Added IOH/IOL per pin group data to
Absolute Maximum Ratings .................................................... 40
Added Table 23 (Total Current Pin Groups) ........................ 40
Revised all timing diagrams for clarity/consistency in Timing
Specifications ........................................................ 42
Updated specifications (reference PCN 09_0173) in the Clock
and Reset Timing section to accurately describe processor cold-
startup/reset timing.................................................. 42
Added tSCLKIW and tSCLK data to Table 42 (Serial Ports—Internal
Clock) ..................................................................61
Added Figure 34 (Serial Port Start-Up with External Clock and
Frame Sync) and Figure 36 (Serial Ports—Enable and Three-
State) ............................................................................................62
To view product/process change notifications (PCNs) related to
this data sheet revision, please visit the processor's product page
on the www.analog.com website and use the View PCN link.
Added tSUDTE and tSUDRE data to Table 41 (Serial Ports—External
Clock) .................................................................. 61
Rev. C
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Page 2 of 100
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February 2010
ADI [ ADI ]
