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ADSP-21062KS-160 参数 Datasheet PDF下载

ADSP-21062KS-160图片预览
型号: ADSP-21062KS-160
PDF下载: 下载PDF文件 查看货源
内容描述: ADSP- 2106x SHARC DSP单片机系列 [ADSP-2106x SHARC DSP Microcomputer Family]
分类和应用:
文件页数/大小: 48 页 / 368 K
品牌: ADI [ ADI ]
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ADSP-21062/ADSP-21062L  
Link Ports: 2 
؋
 CLK Speed Operation  
from 2 × speed specifications will result in unrealistically small  
skew times because they include multiple tester guardbands. The  
setup and hold skew times shown below are calculated to include  
only one tester guardband.  
Calculation of link receiver data setup and hold relative to link  
clock is required to determine the maximum allowable skew that  
can be introduced in the transmission path between LDATA  
and LCLK. Setup skew is the maximum delay that can be intro-  
duced in LDATA relative to LCLK, (setup skew = tLCLKTWH  
min – tDLDCH – tSLDCL). Hold skew is the maximum delay that  
can be introduced in LCLK relative to LDATA, (hold skew =  
tLCLKTWL min – tHLDCH – tHLDCL). Calculations made directly  
ADSP-21062 Setup Skew = 1.84 ns max  
ADSP-21062 Hold Skew  
= 2.78 ns max  
ADSP-21062L Setup Skew = 2.10 ns max  
ADSP-21062L Hold Skew = 1.87 ns max  
ADSP-21062  
ADSP-21062L  
Max  
Parameter  
Min  
Max  
Min  
Units  
Receive  
Timing Requirements:  
tSLDCL  
tHLDCL  
tLCLKIW  
Data Setup Before LCLK Low  
Data Hold After LCLK Low  
LCLK Period (2 × Operation)  
2.5  
2.25  
tCK/2  
4.5  
4
2.25  
2.25  
tCK/2  
5.25  
4
ns  
ns  
ns  
ns  
ns  
tLCLKRWL LCLK Width Low  
tLCLKRWH LCLK Width High  
Switching Characteristics:  
tDLAHC  
tDLALC  
LACK High Delay After CLKIN High  
18 + DT/2  
6
28.5 + DT/2  
16  
18 + DT/2  
6
29.5 + DT/2  
16  
ns  
ns  
LACK Low Delay After LCLK High1  
Transmit  
Timing Requirements:  
tSLACH LACK Setup Before LCLK High  
tHLACH LACK Hold After LCLK High  
19  
–6.75  
19  
–6.5  
ns  
ns  
Switching Characteristics:  
tDLCLK  
tDLDCH  
tHLDCH  
LCLK Delay After CLKIN  
Data Delay After LCLK High  
Data Hold After LCLK High  
8
2.25  
8
2.25  
ns  
ns  
ns  
ns  
ns  
–2.0  
(tCK/4) – 1  
–2.25  
(tCK/4) – 1  
tLCLKTWL LCLK Width Low  
tLCLKTWH LCLK Width High  
(tCK/4) + 1.25  
(tCK/4) – 1.25 (tCK/4) + 1  
(tCK/4) + 1.5  
(tCK/4) – 1.5 (tCK/4) + 1  
tDLACLK  
LCLK Low Delay After LACK High  
(tCK/4) + 9 (3 × tCK/4) + 16.5 (tCK/4) + 9  
(3 × tCK/4) + 16.5 ns  
NOTE  
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.  
REV. C  
–34–  
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